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Reversible logic has presented with great significance in the recent years because of its characteristics of reduction in power dissipation. Applications of reversible logic circuits lies in the area of Low power CMOS, quantum computing, nanotechnology, DNA computing etc. Wide range of researchers are currently works on sequential and combinational circuits with the help of reversible logic. Decoders are one of the most significant circuits which are used in combinational logic. Various approaches have been proposed for their design. In this article, we have proposed a design of 2:4 decoder. These proposed circuits will be implemented with the help of CMOS BSIM4 model. Proposed design will be efficient in terms of constant inputs, garbage outputs, quantum cost. The reversible logic based design will be implemented and simulated using tanner EDA tool. Performance analysis of the design will be done considering various parameters.

Recent era is immensely concerned on the applications based on “SPATIAL TEMPORAL PROVENANCE (STP)” (i.e)users' check-in behaviors like, people visiting different places at different times of weekdays. Our system is based on providing location identity for mutual persons involving in a distributed transaction. It works under the principle of STAMP (Spatial-Temporal provenance Assurance with Mutual Proofs) scheme in an ad-hoc network that is applicable for the trusted mobile users and WAP(Wireless Access Points)on the android platform. The cryptographic keys are distributed and the users are protected from collusion between each other by a semi-trusted Certificate Authority. Hence in our proposed system, we have introduced a third party to create the STP identity whom both the user's trust derby creating a mutual proof. Providing authentication to the STP identity is done to achieve integrity and non-transferability, giving countermeasures against collusion. The scheme is efficient in terms of storage allocation and computation.

Quantum Dot Cellular automata, one of the emerging nanotechnology is the possible alternative to these problems. This paper presents the comparative analysis of various QCA methodologies used for the implementation of full adder circuit. Also the designs and performance analysis of QCA full adder using Majority gate, minority gate, multilayer wire crossing, 5 input Majority voter gate is discussed. The designs follow the conventional design approaches, but due to the technology differences, they are modified for the best performance in QCA. The layout and simulation results are presented using QCADesigner Tool. QCADesigner is a QCA layout and simulation tool developed at the University of Calgary [1]. Simulations indicate very attractive performance regarding complexity, area, and delay in Minority gate based full adder and 5 input MV gate based full adder.

In this paper the concept of low power technology and Nanoelectronics is used while implementing the reversible logic based parity checker and parity generator circuits using Quantum Dot Cellular Automata Combination of reversible logic and quantum dot cellular automata technology provides the resultant circuit whose size is extremely small as well as the power consumption in the circuit is very less. In this paper single layered reversible parity generator and checker circuit is proposed. This parity checker and parity generator circuits are designed using efficient reversible XOR gate. Here efficient design of QCA based Feynman gate is used for the implementation of the circuits. In digital communication, a large amount of data is transmitted and received across various mediums. When data is transferred noise gets added to it which makes signal recovery very difficult. Parity bit is used to recover the signal. Parity bit is known as very common error detection code in the data transmission system. Comparative analysis of proposed reversible circuits like Parity Generator and Parity Checker Circuits are efficient in terms of area, complexity and latency and wire crossings. QCADesigner 2.0.3 tool is used for implementation of these circuits.

Quantum Dot Cellular Automata has attracted a lot of attention due to its extremely small feature size and ultra low power consumption. It is a possible alternative for transistor based technology. This paper presents the Single Layered design and construction of Logic Generator Block which generates the logic of various devices like 1-Bit comparator, 1- Bit Half Adder, 1-Bit Half Subtractor, AND gate, XOR gate, NOR gate and XNOR gate. Proposed design is cost effective and easy to fabricate due to absence of wire crossings. This block can be made more efficient by using control lines. Depending on individual value on control line, logic of individual device will be generated. QCADesigner 2.0.3 tool is used for design and simulation of Logic Generator Block.

Quantum Dot Cellular Automata is one of the six emerging technology which can overcome the limitations of current transistor based technology. Quantum Dot Cellular Automata is popular technology due to its extremely small feature size and ultra low power consumption. In this paper new XOR gate using Coupled Majority Voter Minority gate is proposed. Using this proposed XOR gate Binary to Gray Code and Gray to Binary Code Converters are designed. This paper shows the performance analysis of Proposed XOR circuit and it has been proved that XOR gate and Binary to Gray and Gray to Binary Code converters are efficient in terms of area, complexity, latency and wire crossings. QCADesigner 2.0.3 tool is used for design and simulation of these circuits.