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Convolutional Neural Networks (CNNs) have shown outstanding accuracy for many vision tasks during recent years. When deploying CNNs on portable devices and embedded systems, however, the large number of parameters and computations result in long processing time and low battery life. An important factor in designing CNN hardware accelerators is to efficiently map the convolution computation onto hardware resources. In addition, to save battery life and reduce energy consumption, it is essential to reduce the number of DRAM accesses since DRAM consumes orders of magnitude more energy compared to other operations in hardware. In this paper, we propose an energy-efficient architecture which maximally utilizes its computational units for convolution operations while requiring a low number of DRAM accesses. The implementation results show that the proposed architecture performs one image recognition task using the VGGNet model with a latency of 393 ms and only 251.5 MB of DRAM accesses., Comment: 4 pages

Convolutional Neural Networks (CNNs) are often the first choice for visual recognition systems due to their high, even superhuman, recognition accuracy. The memory configuration of CNN accelerators highly impacts their area and energy efficiency, and employing on-chip memories such as SRAMs is unavoidable. SRAMs can reduce the number of energy-hungry DRAM accesses by storing a large amount of data locally. In this paper, we propose a new on-chip memory configuration, for a certain class of CNN accelerators that divides the memories into two groups. The first group consists of shallow but wide SRAMs into which parallel computational units accumulate intermediate results. The second group includes narrow but deep SRAMs shared between adjacent computational units to store then transfer final results to the external DRAM without interrupting the computation process. Implementation results show that the proposed configuration reduces the area by 21 % and improves the energy efficiency by 18% compared to designs which use an ordinary ping-pong structure for SRAM-DRAM data transfer.

Convolutional Neural Networks (CNNs) have achieved significant success in image classification. One of the main reasons that CNNs achieve state-of-the-art accuracy is using many multi-scale learnable windowed feature detectors called kernels. Fetching of kernel feature weights from memory and performing the associated multiply and accumulate computations consume massive amount of energy. This hinders the widespread usage of CNNs, especially in embedded devices. In comparison with CNNs, decision forests are computationally efficient since they are composed of decision trees, which are binary classifiers by nature and can be implemented using AND-OR gates instead of costly multiply and accumulate units. In this paper, we investigate the migration of CNNs to decision forests as one of the promising approaches for reducing both execution time and power consumption while achieving acceptable accuracy. We introduce POLYCiNN, an architecture composed of a stack of decision forests. Each decision forest classifies one of the overlapped sub-images of the original image. Then, all decision forest classifications are fused together to classify the input image. In POLYCiNN, each decision tree is implemented in a single 6-input Look-Up Table and requires no memory access. Therefore, POLYCiNN can be efficiently mapped to simple and densely parallel hardware designs. We validate the performance of POLYCiNN on the benchmark image classification tasks of the MNIST, CIFAR-10 and SVHN datasets.

High-Level Synthesis (HLS) brings FPGAs to audiences previously unfamiliar to hardware design. However, achieving the highest Quality-of-Results (QoR) with HLS is still unattainable for most programmers. This requires detailed knowledge of FPGA architecture and hardware design in order to produce FPGA-friendly codes. Moreover, these codes are normally in conflict with best coding practices, which favor code reuse, modularity, and conciseness. To overcome these limitations, we propose Module-per-Object (MpO), a human-driven HLS design methodology intended for both hardware designers and software developers with limited FPGA expertise. MpO exploits modern C++ to raise the abstraction level while improving QoR, code readability and modularity. To guide HLS designers, we present the five characteristics of MpO classes. Each characteristic exploits the power of HLS-supported modern C++ features to build C++-based hardware modules. These characteristics lead to high-quality software descriptions and efficient hardware generation. We also present a use case of MpO, where we use C++ as the intermediate language for FPGA-targeted code generation from P4, a packet processing domain specific language. The MpO methodology is evaluated using three design experiments: a packet parser, a flow-based traffic manager, and a digital up-converter. Based on experiments, we show that MpO can be comparable to hand-written VHDL code while keeping a high abstraction level, human-readable coding style and modularity. Compared to traditional C-based HLS design, MpO leads to more efficient circuit generation, both in terms of performance and resource utilization. Also, the MpO approach notably improves software quality, augmenting parametrization while eliminating the incidence of code duplication., 9 pages. Paper accepted for publication at The 27th IEEE International Symposium on Field-Programmable Custom Computing Machines, San Diego CA, April 28 - May 1, 2019

Deep Neural Networks (DNNs) have gained significant popularity in several classification and regression applications. The massive computation and memory requirements of DNNs pose special challenges for FPGA implementation. Moreover, programming FPGAs requires hardware-specific knowledge that many machine-learning researchers do not possess. To make the power and versatility of FPGAs available to a wider DNN user community and to improve DNN design efficiency, we introduce a Single hidden layer Neural Network (SNN) multiplication-free overlay architecture with fully connected DNN-level performance. This FPGA inference overlay can be used for applications that are normally solved with fully connected DNNs. The overlay avoids the time needed to synthesize, place, route and regenerate a new bitstream when the application changes. The SNN overlay inputs and activations are quantized to power-of-two values, which allows utilizing shift units instead of multipliers. Since the overlay is a SNN, we fill the FPGA chip with the maximum possible number of neurons that can work in parallel in the hidden layer. On a ZYNQ-7000 ZC706 FPGA, it is thus possible to implement 2450 neurons in the hidden layer and 30 neurons in the output layer. We evaluate the proposed architecture on typical benchmark datasets and demonstrate higher throughput with respect to the state-of-the-art while achieving the same accuracy.

We investigate a deep learning methodology that can produce more accurate behaviors for autonomous vehicles with a much smaller amount of training data than by using supervised learning alone. In this paper, we develop a Correction-Based Incremental Learning (CBIL) algorithm that adds additional training examples strategically selected from cases where the autonomous vehicle has made mistakes, and is repeated over multiple iterations to dramatically improve mean time to failure. CBIL can be thought of as an online mistake bound learning model that reduces the number of training examples needed to define robust decision boundaries, and is trained offline to solve the problem of catastrophic forgetting. We quantitatively benchmark the performance of CBIL using several experiments related to autonomous platooning performed in truck driving simulations and in the laboratory with mobile robots.

Deep Neural Networks (DNNs) and Convolutional Neural Networks (CNNs) have gained significant popularity in several classification and regression applications. The massive computation and memory requirements of deep NN architectures pose particular challenges for their FPGA implementation. Moreover, programming FPGAs requires hardware-specific knowledge that many machine-learning researchers do not possess. To make the power and versatility of FPGAs available to a wider deep learning user community and to improve DNN design efficiency, we introduce POLYBiNN, a scalable and efficient combinatorial inference engine for DNNs and CNNs. POLYBiNN is composed of a stack of decision trees, which are binary classifiers by nature, and utilizes AND-OR gates instead of multipliers and accumulators. POLYBiNN drastically cuts the hardware consumption down while maintaining high accuracy, and it is a memory free inference engine. We also propose a tool that generates automatically a low-level hardware description of the trained POLYBiNN for a given application. We evaluate POLYBiNN for the MNIST dataset when implemented in a ZYNQ-7000 ZC706 FPGA platform. The system achieves a throughput of up to 100 million image classifications per second with 90 ns latency on the MNIST dataset with 97.18% accuracy. The power consumption of PLOYBiNN is less than 1.2 W. We also show how POLYBiNN can be used in the fully connected layers of a CNN and apply this approach to the CIFAR-10 dataset.

Convolutional neural networks (CNNs) are responsible for many recent successes in the computer vision field and are now the dominant approach for image classification. However, CNN-based methods perform many convolution operations and have high power consumption which makes them difficult to deploy on mobile devices. In this paper, we propose a new method to reduce CNN power consumption by simplifying computations before max-pooling layers. The proposed method estimates the output of the max-pooling layer by approximating the preceding convolutional layer with a preliminary partial computation. Then, the method performs a complementary computation to generate an exact convolution output only for the selected feature. We also present an analysis of the approximation parameters. Simulation results show that the proposed method reduces the power consumption by 21% and the silicon area by 19% with negligible degradation in classification accuracy for the CIFAR−10 dataset.

The emergence of 5G networks and real-time applications across networks has a strong impact on the performance requirements of IP lookup engines. These engines must support not only high-bandwidth but also low-latency lookup operations. This paper presents the hardware architecture of a low-latency IPv6 lookup engine capable of supporting the bandwidth of current Ethernet links. The engine implements the SHIP lookup algorithm, which exploits prefix characteristics to build a compact and scalable data structure. The proposed hardware architecture leverages the characteristics of the data structure to support low-latency lookup operations, while making efficient use of memory. The architecture is described in C++, synthesized with a high-level synthesis tool, then implemented on a Virtex-7 FPGA. Compared to other well-known approaches, the proposed IPvThe emergence of 5G networks and real-time applications across networks has a strong impact on the performance requirements of IP lookup engines. These engines must support not only high-bandwidth but also low-latency lookup operations. This paper presents the hardware architecture of a low-latency IPv6 lookup engine capable of supporting the bandwidth of current Ethernet links. The engine implements the SHIP lookup algorithm, which exploits prefix characteristics to build a compact and scalable data structure. The proposed hardware architecture leverages the characteristics of the data structure to support lowlatency lookup operations, while making efficient use of memory. The architecture is described in C++, synthesized with a highlevel synthesis tool, then implemented on a Virtex-7 FPGA. Compared to the proposed IPv6 lookup architecture, other wellknown approaches use at least 87% more memory per prefix, while increasing the lookup latency by a factor of 2.3×.6 lookup architecture reduces lookup latency by a factor of 2.3x and uses as much as 46% less memory per prefix for a synthetic prefix table holding 580 k entries.

To perform accurate and smooth behaviors in dynamic environments with moving objects, robotic visuomotor control should include the ability to process spatio-temporal information. We propose a system that uses a spatio-temporal deep neural network (DNN), with video camera pixels as the only input, to handle all the visual perception and visuomotor control functions needed to perform robotic behaviors such as leader following. Our approach combines: (1) end-to-end deep learning for inferring motion control outputs from visual inputs, (2) multi-task learning for simultaneously producing multiple control outputs with the same DNN, and (3) spatio-temporal deep learning for perceiving motion across multiple video frames. We use driving simulations to quantitatively show that spatio-temporal DNNs increase driving accuracy and driving smoothness by improving machine perception of scene kinematics. Experiments conducted with mobile robots in a laboratory test track show real-time embedded systems performance comparable to human reaction times to visual stimuli, and indicate that a spatio-temporal deep learning robot is able to follow a leader for long periods of time, while keeping within lanes and avoiding obstacles.

String matching hardware engines generally utilize Ternary Content Addressable Memories (TCAMs). Although TCAM-based solutions are fast, they are expensive and power hungry. This paper proposes a high-performance memory-less architecture for string matching called Split-Bucket. It offers a performance comparable to TCAM-based solutions. Moreover, it is reconfigurable and scalable to the size of the target string set and the width of the string. The architecture is characterized using the Longest Prefix Match problem for IP address lookup and is implemented on a Virtex-7 FPGA. For a real-world routing table with 524 k IPv4 prefixes, the Split-Bucket architecture achieves a throughput of 103.4 M packets per second and consumes 23% and 22% of the Look Up Tables and Flip-Flops of a Xilinx XC7V2000T chip, respectively.

Efficient implementation of non-linear activationfunctions is essential to the implementation of deep learningmodels on FPGAs. We introduce such an implementation basedon the Discrete Cosine Transform Interpolation Filter (DCTIF). The proposed interpolation architecture combines simple arithmeticoperations on the stored samples of the hyperbolic tangentfunction and on input data. It achieves almost 3 better precisionthan previous works while using a similar amount computationalresources and a small amount of memory. Various combinationsof DCTIF parameters can be chosen to trade off the accuracy andthe overall circuit complexity of the tanh function. In one case, the proposed architecture approximates the hyperbolic tangentactivation function with 0.004 maximum error while requiringonly 1.45 kbits BRAM memory and 21 LUTs of a Virtex-7 FPGA.

This paper presents the design of pipelined IEEE 754-2008 decimal floating-point (DFP) multipliers targeting FPGAs. A key component of the architecture is the fixed-point multiplier function which impacts the overall performance and area utilization. In this paper, we propose a new method to realize this operation by carefully organizing the partial products and developing an algorithm for binary-decimal compression. The DFP multipliers with 5 to 12 pipeline stages are coded in VHDL and implemented on a Xilinx Virtex-5 FPGA. The overall design is compared with another approach based on fixed-point multipliers using a BCD-4221 compression technique. Using post layout extracted design data, our approach achieves a delay improvement in the range of 7.9% to 20.3% and an average LUT reduction of 5%.

This paper presents a Zynq-based system to compute Run-Length encoding Matrix features for retinal image texture analysis. In order to improve the performance of the software implementation, we propose a co-processor architecture implemented in the programmable logic portion of the Zynq platform. Experimental results show a speedup of 26.3× with respect to the software version implemented on the ARM processor alone, for 2496 × 1664 images. The additional area to implement the co-processor is limited to 13% of DSP48E1s slices and about 2% for LUTs and flip-flops.

This paper proposes a method to optimize application-specific microprocessors for fixed-point computations. Fixed-point word-length optimization is a well-known research area that aims to find the optimal trade-offs between accuracy and hardware cost in bitwidth allocation signals in fixed point circuits. This work proposes a methodology to combine word-length optimization with application-specific processor customization. The goal is to optimize the following parameters in the processor architecture: (1) datatype word-lengths, (2) size of register-files and (3) architecture of the functional units. Multi-level evolutionary algorithms are employed to perform the optimization. To facilitate evaluation, a new processor design environment was developed that supports necessary customization flexibility to realize and evaluate the proposed methodology. The experimental results show that for five evaluated benchmarks, the proposed methodology can reduce the number of consumed LUTs and flip-flops by an average of 11.9% and 5.1%, respectively, while reducing the latency by an average of 33.4%.

This paper presents a reliable non-blind method to measure intrinsic lens blur. We first introduce an accurate camera-scene alignment framework that avoids erroneous homography estimation and camera tone curve estimation. This alignment is used to generate a sharp correspondence of a target pattern captured by the camera. Second, we introduce a Point Spread Function (PSF) estimation approach where information about the frequency spectrum of the target image is taken into account. As a result of these steps and the ability to use multiple target images in this framework, we achieve a PSF estimation method robust against noise and suitable for mobile devices. Experimental results show that the proposed method results in PSFs with more than 10 dB higher accuracy in noisy conditions compared with the PSFs generated using state-of-the-art techniques.

This paper reviews how the evolution of FDSOI planar architecture towards Trigate Nanowires leads to a natural Single Electron Transistor and Field Effect Transistor convergence at room temperature. On one hand, this convergence sets up technological specifications to preserve CMOS operation. On the other hand it opens the path to room temperature hybrid circuits based on single electron transistors and MOSFETs. Further on, single electron effects can be downscaled to the ultimate single atom transistors and we demonstrate the practical performance of electron pumps for metrologic applications.

The Sparse Matrix-Vector multiplication (SpMV) is an algorithm used in many fields. Since the introduction of CUDA and general purpose programming on GPUs, several efforts to optimize it have been reported. SpMV optimization is complex due to irregular memory accesses depending on the nonzero element distribution of the matrix. In this paper, we propose a model that predicts the number of memory transactions of SpMV for a matrix stored in the CSR format. With the number of memory transactions known in advance, the performance and the execution time can be estimated. The model can be used to select the best suited CUDA implementation for sparse matrices for a given application domain. Predicted results from the model are within 7.5% for the matrices of more than 1000 rows that we have tested on the NVIDIA Tesla K20c and Ge-Force GTX 670.

This paper presents a novel approach for automatic detection of microaneurysms and haemorrhages in fundus images. First, it begins with a preprocessing stage for shade correction, contrast enhancement and denoising. Second, all regional minima with sufficient contrast are extracted and considered as candidates. Third, in an image flooding scheme, a new set of dynamic shape features is computed as a function of intensity. Finally, a Random Forest classifies the candidates into lesions and non lesions. A set of 143 fundus images with an average of 2210 pixels in diameter was acquired using different cameras and used for training and testing. The proposed approach achieved a global score over the FROC curve of 0.393, while previous work with images of similar resolution reported a score of 0.233., 2014 IEEE 11th International Symposium on Biomedical Imaging, ISBI 2014, 29 April-2 May, 2014, Beijing, China

Thanks to a well-controlled CMOS FDSOI technology we have recently been able to demonstrate breakthroughs in the combined use of field effect and Coulomb blockade phenomena. On one hand, we have demonstrated room temperaturehybrid circuits based on single electron transistors and MOSFETs. On the other hand, we have shown the practical performance of electron pumps designed with a single silicided Coulomb island and MOSFETs as tunable barriers for metrologic applications.

This paper introduces a new approach for finite-precision error modeling based on affine arithmetic. The paper demonstrates that there is a common hazard in affine arithmetic-based error modeling methods described in the literature. The hazard is linked to early substitution of the signal terms that emerge in operations such as multiplication and division. The paper proposes postponed substitution combined with function maximization to address this problem. The paper also proposes a modification in the error propagation process to enhance the error modeling accuracy. An existing word length optimization method is reproduced to evaluate the efficiency of this modification. The results demonstrate that the proposed modification can improve the hardware area results by up to 7.0% at the expense of negligible complexity overhead.

We access properties of single dopants embedded in ultra-scaled MOSFET. In such nanostructures, the ionization energy of a single dopant is enhanced. We establish a new method to determine the energy spectrum of a single dopant by connecting two dopants in series and using one dopant as an energy probe for the second one. Gigahertz microwave driving of this double donor system reveals coherent charge transfert in this ultimate “atomic” transistor.

This paper introduces a framework to develop and characterize digital circuits using Carbon Nanotube Field Effect Transistors (CNFET). We define a 4-step process that involves design capture, pre-processing, circuit simulation and results extraction and interpretation. The initial work leading to this framework involves the selection of appropriate CNFET model and model parameters, and determination of optimized substrate voltage. Through a set of custom-design automated scripts, various logic gates were simulated, data were compiled and characterization results were obtained. A complete approximate squarer circuit was also designed, implemented and characterized using the framework. To demonstrate the power of Carbon Nanotube technology, the same circuit was also implemented in 16 nm CMOS technology for comparison. An improvement by factor of 17× in PDP was achieved with CNT.

Tone-mapping (TM) aims to adapt high dynamic range images to conventional display devices. TM algorithms are usually implemented on general purpose processors and graphics processing units. Such platforms may not meet performance, area, power and flexibility constraints imposed by the embedded system domain. This paper presents the design and implementation of a customized processor for a global TM algorithm. Using an architecture description language, three custom instructions to calculate luminance, logarithm and maximum luminance were added to a 32-bit RISC-based processor. The logarithm was computed using an improved Mitchell approximation. Experimental results demonstrate a 169% performance improvement when adding all three instructions, with a hardware overhead of only 22%.

Particle filters have been widely used for video tracking due to their robustness. However, most particle filter algorithm implementations are computationally expensive which makes them ill-suited for real-time embedded systems. There have been some attempts to provide hardware implementations for the particle filter, but none of them tried to simplify the algorithm first in order to make it more efficient for the hardware implementation. In this paper, a new sampling algorithm inspired from the particle filter methodology is proposed. It includes a resampling scheme that uses a new method to assign the number of particles between filter iterations and a criterion to reduce the number of processed samples, both in order to reduce the computational burden. Our experiments demonstrate that the algorithm can be as accurate as the CONDENSATION algorithm, while reducing the computational load by a factor of 30%.

Determining the motion pattern of laboratory animals is very important in order to monitor their reaction to various stimuli. In this paper, we propose a robust method to track animals, and consequently determine their motion pattern. The method is designed to work under uncontrolled normal laboratory conditions. It consists of two steps. The first step tracks the animal coarsely, using the combination of four features, while the second step refines the boundaries of the tracked area, in order to fit more precisely the boundaries of the animal. The method achieves an average tracking error smaller than 5% for our test videos.

This paper presents a fine-grained configurable processor model used to generate image processing Application Specific Instruction Set Processors (ASIPs). A methodology to develop a minimal instruction set ASIP with the processor model is also proposed. The methodology is based on using specialized instructions in conjunction with Instruction Set Architecture (ISA) subsetting to reduce hardware costs and improve execution time. The performance of an FPGA implementation of the proposed processor model is measured for a two-dimensional Gaussian filter and results are compared to a popular commercial soft core processor. With ISA subsetting and specialized instructions, the proposed processor uses up to 45% fewer slices while achieving a 1.57× speedup.

Image contrast enhancement methods play a key role in many image processing and vision applications. For surveillance applications, real-time contrast improvement over the whole image is required when videos are taken in poor lighting conditions. It is also necessary to highlight details in shadowed regions without introducing artifacts. In this paper, several state-of-the-art contrast enhancement methods are compared. Image quality is evaluated by means of objective metrics such as intensity contrast and brightness error, and by subjective assessment. Execution time is also measured. Experimental results show that a technique based on histogram modification presents a better trade-off considering both aspects.

Although single dopant signatures have been observed at low temperature [1–2], the impact on transistor performance of a single dopant atom at room temperature is not yet well understood. Here, for the first time, we provide an in-depth understanding of single dopant influence on NMOSFETs characteristics by linking low and room temperature transport. We demonstrate that, for gate length of 30 nm and below (channel length down to 10 nm), the presence of a single dopant dramatically alters the subthreshold behaviour when the dopant is located in the middle of the channel. Moving the dopants away from the channel leads to enhanced variability above the threshold voltage V t .

We show the first measurements of a silicon electron pump produced in an industrial CMOS facility. Sample fabrication derived from state-of-the-art microelectronics processes results in mass production with high yield, very small sizes and easy operation up to high frequencies as these pump do not suffer from cross-capacitance. Further data with metrological assessment will be shown, as well as a a comparison of classical and non-adiabatic pumping modes within the same devices.

We fabricated SOI nanowire MOSFETs with a very small channel volume and few dopants between the highly doped source and drain. The ionization energy of these isolated As dopants can be extracted. We found a much higher energy than calculated value for As in bulk Si. This enhancement is due to the so-called dielectric confinement, because of the proximity of the buried oxide. Transport through this single dopant also enables probing the fluctuations of local density of states in the contacts.

We present techniques used to create a high performance application-specific instruction-set processor (ASIP) implementation of the Pattern-Based Directional Interpolation (PBDI) intra-field deinterlacing algorithm. The proposed techniques focus primarily on an efficient utilization of the available memory bandwidth. They include the use of Very Long Instruction Words (VLIW) and an appropriate choice of custom instructions and application-specific registers in order to form a processing pipeline. We report a speedup factor of 1351 in comparison with a software-only implementation of the algorithm running on a general-purpose 32-bit RISC processor.

This paper presents a design methodology for the implementation of GPS/INS navigation system on Field Programmable Gate Arrays (FPGA). The method proposed in this research is examined using data from three-axis accelerometers and gyroscopes integrated with GPS for a road test experiment in a land vehicle. The designs are described in software which is executed on an embedded microprocessor. Results show that the decentralized closed loop Kalman filter algorithm running on a single precision floating point embedded processor can produce acceptable results relative to those obtained from a desktop PC platform. A first version of the Kalman filter code (used for the optimal integration of INS and GPS) is executed from a 1 MB external SRAM supported by 8 KB of data cache and 4 KB of instruction cache. A second version is run from high speed 64 KB on-chip Block RAM. In the two memory configurations, the maximum sampling frequencies at which the code can be executed are 80 Hz and 119 Hz, respectively, while accelerometer and gyroscope sensors provide data at 75 Hz. Additionally, from the post synthesis timing analyses, the critical frequencies for the two hardware configurations were 63.3 MHz and 83.2 MHz, an enhancement of 26% and 66% respectively over the reference clock of 50 MHz.

This paper presents a design methodology for dedicated real-time video processors. The methodology begins with a basic processor that is progressively morphed into a specialized processor through five systematic steps. It differs from standard methodologies for ASIP design which place exclusive emphasis on the extension of the instruction set. The proposed methodology takes a global look at various processor and system considerations. The last step consists of removing unnecessary functionality from the instruction set. The required flexibility is attained by the use of an architectural description language. We use a basic deinterlacing algorithm to demonstrate the effectiveness of the methodology and present details of the various phases of the design process. Using ELA deinterlacing as a benchmark, the final processor uses 20% fewer logic elements, achieves a global acceleration by a factor of 11, and an improvement in area-delay product of 14, with respect to the basic processor.

We design and fabricate single-electron transistors and electron pumps within an industrial CMOS platform. Based on silicon nanowire transistors, these devices allow very simple and stable single-electron control thanks to doping modulation along the wire.

We investigate the time-dependent transport properties of two very asymmetric coupled quantum dots: a single resonant charge and an electrometer made of a gated silicon nanowire in the Coulomb blockade regime. The occupation probability of the charge trap is obtained by noise measurements. We observe the predicted smearing of the Coulomb peaks at the resonance, the back-action of the electrometer on the single charge as well as a relatively large dip in the charging energy of the whole system.

This paper presents the architecture and FPGA implementation of a video processor for detection and correction of specular reflections in endoscopic images by using an inpainting algorithm. Stream processing and parallelism are used to exceed real-time performance on NTSC format video without the need for an external memory. The system was implemented in a XC2VP30 FPGA and uses 91% of available slices. Image quality is significantly enhanced.

In this paper we propose a new deinterlacing algorithm using motion compensation and directional interpolation. To limit the propagation error that is a major drawback of conventional motion compensated methods, motion estimation is performed using original lines only, for same and opposite parity fields. In addition, a threshold value is used during the search to recognize situations where the motion estimator fails to find an optimal matching block. Enhanced edge-based line average with median filtering is used in these situations. Experimental results show that the proposed method performs better than the traditional motion compensated method, based on objective and subjective criteria.