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True random number generators (TRNGs) play an important role in encryption systems. In this brief, a novel method of generating true random numbers on a field-programmable gate array (FPGA) is proposed based on the random jitter of a multi-stage feedback ring oscillator (MSFRO) as the entropy source. Based on the traditional ring oscillator, a multi-stage feedback structure is added to enlarge the range of clock jitter, and improve the frequency of clock sampling and the randomness of the entropy source. Different from the traditional clock sampling structure, we use the clock jitter signal generated by the MSFRO to sample the clock signal generated by the phase-locked loop (PLL) of the FPGA. The obtained output value is operated by XOR to reduce the deviation of the output value and improve its randomness. The TRNG is implemented in Xilinx Virtex-6 FPGA, which has low hardware resource consumption and high throughput. The entropy source classification, hardware resources and throughput are compared with those of existing TRNGs. The results showed that the proposed TRNG only consumed 24 LUTs and 2 DFFs. Compared with other TRNGs, this design has very low hardware resource consumption and its throughput is up to 290 Mbps. The random bit sequence generated by this TRNG passes the NIST SP800-22 test and the NIST SP800-90B test. [ABSTRACT FROM AUTHOR]

This study presents a pure digital scalable mixed entropy separation structure for the physical unclonable function (PUF) and true random number generator (TRNG), which is implemented on Xilinx field-programmable gate arrays (FPGAs). The mixed entropy separation structure in this study is to solve the problems of unstable output in the existing PUF structure and the poor scalability of the TRNG and PUF design. The proposed design has the following innovations: 1) concept of sensitive entropy and the corresponding processing method are proposed for the first time; 2) design does not need to modify the internal design of the entropy source, and it is suitable for most entropy source arrays; and 3) adjustable PUF bit width and TRNG throughput enhance the scalability of the architecture under different requirements. The structure is simulated and validated on two Xilinx FPGAs and tested under nominal working conditions. The results show that the 512-bit PUF entropy source after treatment is 92.7% more stable than the 1024-bit entropy source before treatment, the random number after treatment passes all types of randomness tests, and the minimum entropy is more than 0.8. Under various conditions within the ranges of 0 °C–80 °C and 0.8–1.2 V, the TRNG output remains stable after treatment; the maximum intra-Hamming distance of the treated PUF is 5.1028%, and the average intra-Hamming distance is 2.7065%. [ABSTRACT FROM AUTHOR]

When the feature size of integrated circuits (ICs) reaches nanometer, nano contaminant particles (CPs) on the surface of semi-finished devices during processing may cause serious device defects, while effective real-time CP detection techniques are still unavailable, especially when the CPs are of low concentration. Using a gold interdigitated electrode fabricated on a ceramics substrate, a sensitive sensor for ultra-trace nano CP detection in cleaning fluids is developed, which employs an optimized detection signal integrating the nanofluidic enrichment of nanoparticles (NPs) into interfacial capacitance measurement. The detection can achieve a limit of detection of 102 particles/mL with a response time of 30 s. The logarithmic linear range of this sensor reaches (102 - 107) particles/mL for CPs of 10 nm in grain diameter, which can meet the test demand of practical concentration. This sensor has capability to detect CPs of different material and size, and the operation is real-time and nondestructive. In addition, it is demonstrated to work reliably in solutions with different conductivity. The detection protocol is simple, and the sensor as well as the impedance analyzer for test also has advantages in portability and cost efficiency for industrial-scale on line application. This work provides a feasible and promising approach for IC fabrication’s quality evaluation through ultra-trace nano CP detection in used cleaning liquid samples. [ABSTRACT FROM AUTHOR]

Here, we demonstrate a novel 2-D–3-D graphene (Gr)/MoS2/Si nanowires Schottky-NP bipolar van der Waals heterostructure, which allows the combination of the unique properties of 2-D layered materials with the proven merits of well-developed silicon technologies. Significantly, the resultant devices exhibit an ultrahigh response speed of 17 ns with a broad spectral response characteristic, which represents most fast response for 2-D transition metal dichalcogenide (TMD)-based photodetectors and is comparable to that of commercial Si photodetectors. A high responsivity of 0.6 A $\text{W}^{-{1}}$ and a detectivity of ${8}\times {10}^{{12}}$ Jones are also achieved. This result suggests a pathway for the fabrication of high-speed photodetectors based on TMDs. [ABSTRACT FROM AUTHOR]

This paper presents a methodology for accurate characterization of Single Event Transient (SET) propagation in SRAM-based Field Programmable Gate Arrays (FPGAs): both generation and measurement of SETs are implemented on chip, respectively connected to input port and output port of the test combinational paths. The scheme we developed is mainly based on two circuits: 1) the one is a SET generating circuit for on-chip producing an adjustable pulse with a temporal resolution of near 100 ps; 2) the other is a SET measuring circuit for on-chip measuring pulses with a temporal resolution of near 80 ps and the ability to detect narrow transient pulses of about 300 ps. Based on above methodology, we investigate the effect of traversing seven logic chains with different gate types and multiple chain lengths on pulse widths, i.e., Propagation Induced Pulse Distorting (PIPD). Results demonstrate, when SETs propagate along Look Up Tables (LUTs) in Virtex-6 FPGAs, there is a broadening for negative SETs (1-0-1) while not for positive SETs (0-1-0); in addition, pulse width has no impact on PIPD, and which is linearly proportional to the number of stages. [ABSTRACT FROM AUTHOR]