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Fog computing has been an effective paradigm of real-time applications in the IoT area, which enables task offloading at network edge devices. Particularly, many emerging vehicular applications require real-time interaction between the terminal users and computation servers, which can be implemented in fog-based architecture. However, it is still challenging to apply fog computing in vehicular networks due to high mobility of vehicles and uneven distribution of vehicle density, which may result in performance degradation, such as unbalanced workload and unexpected task failure. In this article, we investigate a new service scenario of task offloading under a three-layer service architecture, where the resources of vehicular fog (VF), fog server (FS), and central cloud (CC) are utilized in a cooperative way. On this basis, we formulate the probabilistic task offloading (PTO) problem by synthesizing task transmission, computation, and result retrieval, as well as characterizing the heterogeneity of computation servers. The objective of the PTO is to minimize the weighted sum of execution delay, energy consumption, and payment cost. To resolve the PTO problem, we propose a comprehensive task offloading algorithm by combining the alternating direction method of multipliers (ADMMs) and particle swarm optimization (PSO), called ADMM-PSO. The basic idea of the ADMM-PSO is to divide the PTO problem into multiple unconstrained subproblems and achieve the optimal solution in the form of an iterative coordination process. For each iteration, the solution is achieved by solving each subproblem with the PSO and updated based on a designed rule, which is able to converge to the optimal solution when the stop criterion is satisfied. Finally, we build the simulation model and implement the proposed algorithm for performance evaluation. The simulation results demonstrate the superiority of the proposed algorithm under a wide range of service scenarios. [ABSTRACT FROM AUTHOR]

Time-to-digital converters (TDCs) using dedicated carry chains of field programmable gate arrays (FPGAs) are usually organized in tapped-delay-line type which are intensively researched in recent years. However this method incurs poor differential nonlinearity (DNL) which arises from the inherent uneven bin granularity. This paper proposes a TDC architecture which utilizes the carry chains in a quite different manner in order to alleviate this long-standing problem. Two independent carry chains working as the delay lines for the fine time interpolation are organized in a ring-oscillator-based Vernier style and the time difference between them is finely adjusted by assigning different number of basic delay cells. A specific design flow is described to obtain the desired delay difference. The TDC was implemented on a Stratix III FPGA. Test results show that the obtained resolution is 31 ps and the DNL\INL is in the range of (−0.080 LSB, 0.073 LSB)\(−0.087 LSB, 0.091 LSB). This demonstrates that the proposed architecture greatly improves linearity compared to previous techniques. Additionally the resource cost is rather low which uses only 319 LUTs and 104 registers per TDC channel. [ABSTRACT FROM PUBLISHER]