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A wide-input-range DC–DC-based dimmable LED driver is presented in this paper. The proposed LED driver can be automatically configured to operate in the soft-switching mode under the high-voltage condition in order to minimize the converter’s dominant switching power loss. Adaptive resonant timing control is developed to enable proper dead-time generation for on-chip high-voltage power FETs in both hard- and soft-switching modes under different input and output voltages for the power loss minimization. In the proposed LED driver, two low-power body-diode-based zero-voltage detectors and an adaptive resonant timing emulator are also proposed for providing accurate and high-speed zero-voltage switching (ZVS) detection of both power FETs, and achieving optimal quasi-ZVS condition, respectively. Implemented in a 0.5 \mu \text m HV CMOS process, the proposed buck-based LED driver can support an input voltage range from 5 V to 115 V and up to 25 series-connected high-brightness LEDs with the maximum output power of 25 W. The LED driver can operate up to 1.6 MHz in the soft-switching mode and 2.2 MHz in the hard-switching mode for providing the peak power efficiencies of 94.4% and 93.6%, respectively. Compared with the state-of-the-art counterparts, this work is the only integrated DC–DC-based dimmable LED driver to demonstrate auto-configurable hard- and soft-switching capability achieving high power efficiency and current accuracy over the widest input voltage range and the largest number of series-connected output LEDs. [ABSTRACT FROM PUBLISHER]

This paper presents an integrated buck-type dimmable synchronous LED driver for high-brightness solid-state lighting applications. A glitch-tolerant synchronous current control (GT-SCC) scheme is proposed to regulate the average LED current. The GT-SCC enables fast settling time of the LED current upon start-up or PWM dimming condition, and provides reliable operation under high dV/dt slewing during switching transitions of the LED driver. The proposed LED driver consists of a high-speed low-power HV synchronous gate driver to enable on-chip synchronous rectification with a dual-nMOS power train under different input voltages for the conduction power loss reduction. Two on-chip senseFET peak and valley current sensors are also developed to offer low-power and reliable current sensing under high input voltages. Implemented in a 0.35 \mum 50 V CMOS process, the proposed LED driver supports a wide input range from 5 V to 45 V, operates up to 4 MHz with a small-value inductor of 8.2 \muH, handles a high PWM dimming frequency of 20 kHz with a wide duty-ratio range from 0.1 to 1, and delivers an average LED current of 700 mA for driving up to 12 series-connected HB-LEDs (with the maximum output power of 26 W). The proposed LED driver achieves a peak power efficiency of 97.2% and the current deviation \leq\pm 3.3% of the average LED current under different conditions. The worst-case settling time achieves 3.2 \mus that is at least 2.7 times improvement over state-of-the-art counterparts. [ABSTRACT FROM AUTHOR]

Two integrated high-speed gate drivers to enable high-frequency operation of synchronous rectifiers in high-voltage switching power converters are presented in this paper. The first synchronous gate driver for a CMOS power train consists of a capacitively coupled level shifter (CCLS) that offers negligible propagation delays and no static current consumption, and requires only one off-chip capacitor to enable high-side power pMOS driving capability without any external floating supply. The second synchronous gate driver consists of a low-power high-speed dynamically controlled level shifter (DCLS) with a reliability-enhanced error-suppression technique for driving a dual-nMOS power train. In addition, a dynamic timing control (DTC) is developed to generate proper dead time for power FETs in order to enable soft switching operation of the converter under different input voltages for enhancing the converter reliability. The converter power efficiency can be also improved by minimizing both switching and short-circuit power losses under high-input-voltage conditions. Implemented in a 0.5 µm 120 V CMOS process, both proposed CCLS and DCLS have demonstrated to shift up 5 V signal to 100 V and 40 V, respectively, improving the FoM by at least 10 times and 2.9 times compared to respective state-of-the-art level shifters. The DTC circuit enables proper ZVS operation in a synchronous buck converter with the CCLS-based gate driver over a wide input supply range from 40 V to 100 V, providing a converter maximum power-efficiency improvement of 11.5%. [ABSTRACT FROM AUTHOR]

This paper presents a floating-buck dimmable LED driver for solid-state lighting applications. In the proposed driver, an adaptive timing difference compensation (ATDC) is developed to adaptively adjust the off-time of the low-side power switch to enable the driver to achieve high accuracy of the average LED current over a wide range of input voltages and number of output LED loads, fast settling time, and high operation frequency. The power efficiency benefits from the capabilities of using synchronous rectifier and having no sensing resistor in the power stage. The synchronous rectification under high input supply voltage is enabled by a proposed high-speed and low-power gate driver with pseudo-digital level shifters. Implemented in a 0.35 \mum 50 V CMOS process, experimental results show that the proposed LED driver can operate at 1 MHz and achieve peak power efficiency of 93% to support a wide range of series-connected output LEDs from 1 to 10 and a wide input range from 10 to 40 V. The proposed LED driver has only 2.8% current error from the average LED current of 345 mA and settles within 8.5 \mus after triggering the dimming condition, improving the settling time by 14 times compared with the state-of-the-art LED drivers. [ABSTRACT FROM AUTHOR]