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In this brief, a new low-voltage high-precision bidirectional input current squarer/divider based-full wave rectifier circuit is presented. The designed current squarer is based on a dual translinear loop (DTL) using Floating Gate MOSFET (FGMOS) transistors working in saturation regime. The proposed squarer/divider and rectifier parameters have been evaluated by HSPICE in 180 nm TSMC (level-49) CMOS process. Evaluation outcomes of the designed squarer with VDD=1v shows which the utmost linearity error is 0.28%, the bandwidth is 1.15 GHz, the static and most power dissipation are 20.5 μW and 82 μW, respectively. Also simulation results for rectifier circuit are extracted, which shows that the utmost linearity error is 0.8%, the −3dB bandwidth is 148.4 MHz and the static and most power dissipation are 0.5 μW and 44 μW, respectively. Therewith, to assay the acceptable performance and dependability of the proposed designs Monte Carlo (MC) analysis are accomplished.

This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5 + 5 + 6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a $0.6~\mu m$ standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm $\times6.6$ mm. As for single channel SAR ADC, the area is 0.9mm $\times2.0$ mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.

Clamp-on ultrasonic flowmeters geometry includes four different materials in the ultrasound propagation path: wedge, coupling material, pipe and liquid. In this case, oblique incidence ultrasonic beam generated by the emitter transducer is split into several paths caused by multiple reflections in pipe wall or because of propagation mode conversion at interfaces. These multiple paths are recombined at the reception transducer aperture, producing a single signal whose amplitude and phase depend on which proportion each path contributes. The objective of this paper is to quantify this phenomenon and analyses the implications it has on the accuracy of Clamp-on ultrasonic flowmeters as a function of the fluid that flows inside the pipe. According to simulations, based on 2D ray tracing model and experimental measurements, the variations in the recombination signal at the reception transducer produces a linearity error that in case of the installation under test, Z-mode transducers configuration on PVC pipe, could reach a value of 3.2%.

This paper presents a methodology of calibration to reduce the linearity error of gain in Time amplifier (TA). We divide the input range to several segments and calculate the average of maximum and minimum TA gain in each segment. We also have the checking points to check the width of input interval and decide which segment and corresponding TA gain is for the measured interval. The checking point is the maximum interval in each segment. The input range for each segment is 50 ps, that is, 0–50 ps is the first segment, 50–100 ps is the second segment, and so on. For the TA which the measured range is 700 ps, we divide the range to 14 segments and there is its corresponding TA gain in each segment. The gain error will be reduced from 0.82% to 0.33% and the distortion caused by gain error will be reduced from 5.74 ps to 0.51 ps.

© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This article analyses and explains the implications that dispersive materials have over the linearity in flow measurement when a Clamp-on ultrasonic flowmeter is used. This is of capital importance because dispersive materials are commonly used in the manufacture of transducer wedges and pipes. The evaluation of this phenomenon has been tested by experimental measurement. The used setup consisted of a water flow calibration facility where a commercial Clamp-on ultrasonic flowmeter was installed on it and its flow measurement was compared with a reference flowmeter. Two experiments have been conducted. A first experiment was performed to evaluate only the effect produced by the fact that the transducer wedge is made of dispersive material. For this reason, an ultrasonic flowmeter was installed on a pipe made of non-dispersive material, in this case, an INOX pipe. Linearity error introduced by the wedge was below 1%. This error complies with the accuracy specification of the ultrasonic flowmeter given by the manufacturer (±1.5%). Finally, a second experiment consisted of installing the ultrasonic flowmeter on a dispersive pipe (PVC pipe) in order to measure the worst condition (both materials, wedge and pipe, were dispersive). Under this condition, the linearity error was increased until it reaches a value of 6.4%. Moreover, in case of a dispersive material pipe, the bigger the pipe thickness is, the bigger non-linearity error is reached.

An optimum boundary design method used in pre-amplifiers stage of interpolation and averaging flash ADC is demonstrated in this work. Without costing a large number of dummy amplifiers and consuming over-range voltage headroom, the proposed technique improves linearity error at the boundary of pre-amplifier offset averaging network. A prototype 8bit flash ADC achieves an 1GSPS sampling speed with a 430mA current consumption in 1.8V supply, the experimental result shows that this optimum method is suitable for high speed flash ADC with interpolation and averaging network.

In the paper design and analysis of an off-axis absolute rotary position sensor setup is described that is intended to use in realizing accurate and reliable absolute angle measurement to be applied in precise control of electric (e.g. vehicle) drives. A solution of using magnetic position sensing elements in combination with two differently magnetized ferromagnetic rings is presented. By assuming a specific setup the algorithm of determining absolute position is given, as well by analyzing the measurement errors, a compensation scheme is elaborated. By using this scheme the linearity error of the sensor setup can significantly be reduced without applying any expensive equipment.

This paper presents a new ultra-low-voltage current-mode four-quadrant analog multiplier. A floating-gate technique is used to provide operating at a supply voltage of 0.75 V for the proposed circuit. PSPICE simulators using 0.18 µm TSMC CMOS process are used to show the workability of the multiplier. Simulation results show that the circuit has a linearity error of 1.5 % for the input current 8 µA, total harmonic distortion of 0.96 % for the input current 8 µA peak and quiescent power consumption of 19.9 µW.

This paper presents a new current-mode squaring circuit. The design is based on MOSFETs translinear principle in strong inversion. A new compensation techniques to minimize the second order effects caused by carrier mobility reduction in short channel MOSFETs is proposed. Tanner T-spice simulation tool is used to confirm the functionality of the proposed design in 0.18μm CMOS process technology. Simulation results indicate that the maximum linearity error is 1.16 % and the power consumption is 331μW.

A novel differential-type magnetic sensor based on the giant magnetoimpedance (GMI) effect, integrating the impedance magnitude and phase characteristics of the amorphous wire due to varying the extern magnetic field, is presented in this paper. The sensor consists of a conditioning circuit based on orthogonal vector lock-in amplifier and differential-type amplifier, and a differential-type sensing head with double sensing elements. Besides, the characteristics of our amorphous wires and the construction of the sensing head are also described in this paper. Especially, a masterly and simple design for integrating the in-phase and quadrature output of orthogonal vector lock-in amplifier utilized in the conditioning circuit is described and analyzed in detail. Multiple measurements show that the sensitivity of the GMI magnetic sensor can achieve about 748 mV/Oe with the full measurement range of ±2.0 Oe, while the linearity error is about 0.92%FS.

A linearization technique for CMOS voltage-controlled oscillators (VCOs) is presented. The linearity of the oscillator is improved by applying a feedback loop using a switched-capacitor network as a frequency-to-voltage converter (FVC). The technique is verified by circuit-level simulation using parameters of a 0.35-µm CMOS technology. After the linearization, the linearity error of VCO can be improved to less than 0.015% for a dynamic range of 60 dB.

An accurate goniometer was constructed being a part of a system devoted to the measurement of reflecting properties of surfaces. By it a surface of the sample under test can be arbitrarily oriented with respect to the observing direction and the direction of the shooting light beam. The high performances (revolution angle uncertainty equal to 0.1deg) required as specifications for the construction are checked. Particular attention is used to analyze the orthogonality among the revolution axes of each goniometer components and their convergence in the goniometer center. The linearity error of each revolution motion is measured by using a differential method. It proves to be effective to highlight the small linearity deviation and to verify the uncertainty declared by the manufacturer

This paper proposed an ultra low-voltage low-power all CMOS exponential V-I converter with tunable input and output ranges. The Taylor series expansion is used for realizing the exponential characteristic. The simulations, based on a 0.25 mum CMOS process, show a 20 dB linear output current range and a 15 dB-linear range with the linearity error less than plusmn 0.5 dB at 1.25V supply voltage. The average power consumption is less than 80 muW

A 6-bit 1.6 GS/s CMOS flash ADC using reversed-reference dummy method is demonstrated in a standard 0.18-μm CMOS process. The proposed method improves linearity error at the boundary of offset averaging networks. The prototype circuit exhibits an INL of +0.32/-0.28 LSB and a DNL of +0.28/-0.28 LSB. The SNDR and SFDR achieve 32 and 44 dB at 1.6 GS/s for Nyquist input frequency. The ADC consumes 350 mW at 1.8 V supply and occupies an active chip area of 0.46 mm2.

A biaxial MEMS raster scanner is developed for laser scanning displays. We discuss microfabrication, packaging, and design aspects, and how to minimize power consumption and linearity error by optimizing the vertical scanner resonant frequency and drive waveform.

A four-quadrant CMOS analogue multiplier is presented. Experimental results show that the multiplier has a dynamic input range, exceeding 60% of the power supply voltage (/spl plusmn/0.5 V), and the linearity error is less than 0.07% at the maximum input range. The simulated maximum power dissipation for the multiplier is 2.83 mW.

A 10-b video CMOS D/A converter for low supply voltage has been developed. Nonsaturating transistors and a new switching scheme are introduced to current sources in the D/A converter, which operates at 50 MS/s with a 2.7 V power supply. Integral linearity error and differential linearity error are less than 0.5 LSB and 0.25 LSB, respectively. The dependence of the linearity error on full-scale voltage is plotted. Device characteristics are summarized. >

A new wide range BiCMOS transconductor and a multiplier were presented. Simulation results show that for a power supply of /spl plusmn/5 V, the linear input range of this transconductor is over /spl plusmn/4 V with the linearity error less than 2%. The total harmonic distortion is less than 0.69% with input range up to /spl plusmn/3 V. Its -3 dB bandwidth is 54 MHz. A new BiCMOS multiplier is also presented. Its linear input range is over /spl plusmn/2.5 V with the linearity error less than 1%. Its -3 dB bandwidth is over 60 MHz. The proposed circuits are expected to be useful in analog signal-processing applications.

A monolithic 14b D/A converter which is self-compensated without trimming analog components will be described. The device has been fabricated with analog compatible I2L technology, affording a linearity error within ± 1/2 LSB or± 0.003%.