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236 results on '"Lin, C H."'

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3. E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology

12. Bottom-up methodology for predictive simulations of self-heating in aggressively scaled process technologies

14. A 7nm CMOS technology platform for mobile and high performance compute application

21. High performance In0.53Ga0.47As FinFETs fabricated on 300 mm Si substrate

22. Ti and NiPt/Ti liner silicide contacts for advanced technologies

24. f2MOVE: fMRI-compatible haptic object manipulation system for closed-loop motor control studies

25. Advanced device performance impact by wafer level 3D stacked architecture

26. Off-state self-heating, micro-hot-spots, and stress-induced device considerations in scaled technologies

27. In0.53Ga0.47As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate

28. A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

30. Study of sub-5 nm RRAM, tunneling selector and selector less device

33. High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

35. The Amorphous-Si CMP process improvement for L14 nm FinFET technology node

42. Speckle contrast reduction by linear and nonlinear photonic devices

44. Effects of BEOL copper CMP process on TDDB for direct polishing ultra-low k dielectric cu interconnects at 28nm technology node and beyond

47. 22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

50. Channel doping impact on FinFETs for 22nm and beyond

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