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17 results on '"Li, Xuwen"'

3. An improved inter-prediction motion estimation algorithm of AVS

Author

Xu Ying, Qiang Wu, Jia Ke-bin, and Li Xuwen

Subjects
Motion compensation, Computational complexity theory, Computer science, Motion estimation, Real-time computing, Worst-case complexity, Algorithm design, Algorithm, Motion vector, Encoder, Data compression
Abstract

Research on inter-prediction algorithms is an important respect in the real-time video codec technology. In the regarded studies, the prediction error can be reduced by incorporating high accuracy estimation and compensation algorithms. So the performance of compressed video can be improved. However, this brings a considerable cost for the complexity of encoder. The computation complexity is mainly due to the complexity of motion estimation. The paper presents an improved algorithm with the initialized searching point prediction, half-stop principle, beforehand skip mode decision, reduced search window and optional search model. This algorithm for the integer-pixel motion estimation is provided to reduce computation complexity in the block-matching process. Experimental results show that the proposed algorithm can reduce about 64%-73% of computation complexity compared to full search but only with little PSNR degradation.

Published
2009
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4. Hardware design of image information processor based on ADSP-TS201 DSPs

Author

Li Xuwen, Gao Qing, Jia Ke-bin, and Qiang Wu

Subjects
business.industry, Computer science, Information processor, Image processing, Logic synthesis, Kernel (image processing), Embedded system, CompactPCI, Hardware_ARITHMETICANDLOGICSTRUCTURES, business, Field-programmable gate array, Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION, Computer hardware, Digital signal processing, PCI Express
Abstract

This paper studies on the hardware design and implementation of a universal multi-DSP and FPGA image information processor in accordance with the PCI-E and CPCI specifications. The image information processor features two clusters of total four ADSP-TS201 TigerSHARC DSPs from ADI as the kernel processing unit, reconfigurable framework implemented by two Xilinx Virtex-5 FXT FPGA chips. Taking full advantage of the high performance, unprecedented I/O bandwidth of TigerSHARC DSP and Virtex-5 FXT FPGA, the processor can easily meet the huge image processing and computing work. The hardware design of high speed Linkport interconnection between TS201 DSPs and FPGA chips is described.

Published
2009
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