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For the first time, we report the positive bias temperature instability of the back gated multilayer MoS2 n-MOSFETs with Al2O3 gate dielectric. In the stress phase, the Id – Vg curve shifts to the positive gate bias. In the recovery phase, it shifts back to the negative gate bias. After 5000 s recovery, it completely recovers to that of the fresh device. The results indicate that the voltage shift is solely due to trapping and detrapping of the pre-existing border traps in the Al2O3 dielectric. The traps consist of fast and slow components with the capture time constants of 7 and 1.8\times 10^2 s and the emission time constants of 15 and 1.0\times 10^3 s, respectively. The results from first-order trapping and detrapping calculations are in overall agreements with 12 measured \Delta Vg curves including six under stress voltages and six in the recovery phases. The energy densities for the fast and slow traps are derived to be in the order of 1013 cm ^-2 eV ^-1 above the bottom of the MoS2 conduction band. [ABSTRACT FROM AUTHOR]

The area, temperature (160–300 K), and bias polarity dependences of the I–V curves of the self-rectifying n+Si-HfO2–Ni resistance random access memory (RRAM) have been measured systematically. The complementary nonrectifying p+Si-HfO2–Ni RRAM I–V data are also provided for reference. To explain all experimental data, three resistances in series in the RRAM device: 1) the Si-HfO2 contact resistance R \(_{\mathrm {Si-HfO}}\) ; 2) the HfO2 dielectric resistance RHfO; and 3) the HfO2– \(Ni\) contact resistance RHfO-Ni must be considered on an equal footing. Previously reported first principle calculation results for the density of states of the monoclinic HfO2 grain boundary with high and low densities of oxygen vacancy V \(_{O}^{0}\) are adopted for describing the conductive filament resistance RHfO of the dielectric at low- and high-resistance states. The temperature dependence of I–V is controlled by three different energy barriers: Schottky-like barrier, multiphonon trap assisted tunneling barrier, and multiphonon deep trap capture barrier (ECAPTURE). It is demonstrated that all experimental data can be explained in a natural and unified way. This model is valuable not only for understanding the conduction mechanism, but also for guiding the future self-rectifying RRAM technology development. [ABSTRACT FROM AUTHOR]

The reliability performance of \Inx\Ga1 - x\As n-MOSFETs with \Al2\O3 gate dielectric under positive-bias temperature instability stress is investigated. The following new phenomena are demonstrated: 1) There are high densities of fast interface traps Nit and slow oxide border traps NSOX near the interface between InGaAs and \Al2\O3. The border traps are more fragile under stress, and therefore, the stress mainly induces border traps. 2) The stress-induced border traps consist of permanent acceptor traps and recoverable donor traps. Acceptor trap energy density \Delta DSOX^\rm Acceptor(E) is mainly distributed above the conduction band edge Ec of InGaAs with a tail extending to the midgap, whereas donor trap energy density \Delta DSOX^\rm Donor(E) has a large distribution inside the InGaAs energy gap with a tail extending to the conduction band. 3) Flicker noise variation after stress and its correlation to the acceptor and donor trap generation and recovery are demonstrated. 4) The recoverable donor traps induce the subthreshold slope and off-current degradation in the stress phase and recover in the recovery phase and also induce continuous degradation of on-current in the recovery phase. The permanent acceptor traps induce the transconductance and on-current degradation. The long-term device lifetime is mainly determined by the generation rate of the acceptor traps. 5) Comprehensive comparison between the Si and InGaAs MOSFETs' degradation behaviors under bias temperature instability stress is presented. The physical recovery of donor oxide traps in dielectric in InGaAs/ \Al2\O3 has never been observed in a Si MOS structure, deserving special attention and further investigation. [ABSTRACT FROM PUBLISHER]

A compact set of equations based on the multiple subbands quasi-ballistic transport theory is developed, and is used to investigate the channel electron effective mobility in recently reported In 0.53Ga0.47As/Al2O3 tri-gate n-FinFET. The extracted electron effective mobility \mun is around 370 cm^2/V·s at low V_g - Vth bias at room temperature and decreases with increasing Vg, and increases with increasing temperature (240–332K). It is very different from the case of Si n-MOSFETs, where the electron mobility decreases with increasing temperature. The low channel effective mobility and the ab-normal temperature dependence of \mun are ascribed to the high acceptor interface trap and border trap energy densities in the conduction band energy of InGaAs. The ballistic channel resistance RBall at low Vds is calculated and compared with the measured channel resistance RCH. The low transmission coefficient T = RBall /RCH \approx 0.06\;to\; 0.05 indicates that there is a large room to improve the InGaAs/Al2O3 n-FinFET performance. [ABSTRACT FROM PUBLISHER]

The reliability performance of \Inx\Ga1-x\As n-type metal–oxide–semiconductor field-effect transistors with \Al2\O3 gate dielectric under positive-bias temperature instability stress is investigated systematically. A model of stress-induced border traps was proposed to interpret all charge pumping and I–V experimental results excellently. The stress-induced border traps include recoverable donor traps and permanent acceptor traps with respective energy densities \Delta DSOX^ \rm Donor(E) and \Delta DSOX^\rm Acceptor(E). The shapes of \Delta DSOX^\rm Donor(E) and \Delta DSOX^\rm Acceptor(E) have been extracted from experimental data. \Delta DSOX^\rm Acceptor(E) mainly distributes in the conduction band of InGaAs with a tail extending to the mid-gap, whereas \Delta DSOX^\rm Donor(E) has a large distribution inside the energy gap and extends to the conduction band. The high density of \Delta DSOX^\rm Donor(E) in the energy gap induces large degradation in the off-current, which is particularly serious when the In composition x is raised to 0.65. [ABSTRACT FROM PUBLISHER]

One of the major problems of p-i-n tunneling field-effect transistor (TFET) is the reliability due to the strong electric field near the tunneling junction. In this paper, using technology computer-aided design simulation, we show that the insertion of a thin n-layer into the tunneling junction of the p-i-n TFET (p-n-i-n TFET) not only enhances its drive current, as has been previously reported, but also improves its reliability. As compared with the conventional p-i-n TFET, we demonstrate the following properties of the p-n-i-n TFET: 1) The normal component of the electric field near the tunneling junction is reduced, and therefore, the field-driven interface-trap generation can be reduced. This can be further reduced by properly aligning the gate electrode with respect to the tunneling junction. 2) The threshold-voltage shift due to the dielectric charge generated near the tunneling junction is significantly reduced. 3) The variation of the threshold voltage to the oxide and bulk thickness variations is also reduced. [ABSTRACT FROM AUTHOR]

A new method is proposed to distinguish the contributions of the low-frequency noise (LFN) from the channel and the source/drain Schottky contacts in MOS devices. The method is applied to back-gated nMOSFETs with MoS2 channel and Al2O3 gate dielectric. To avoid a possible noise signal contamination from the top MoS2 surface by oxygen or water molecules absorption, the nMOSFETs with multilayer MoS2 are fabricated, and the measurements are carried out in the vacuum. The trap density Not at the MoS2/Al2O3 interface is derived for the first time using the proposed method. It is found that the Not responsible to LFN depends strongly on the surface potential, ranging from 4\times 10^10 cm ^\mathrm -2 in the weak over-drive region to 5\times 10^11 cm ^\mathrm -2 in the strong over-drive region. [ABSTRACT FROM AUTHOR]

We present a systematic study of tunneling leakage current in metal gate MOSFETs and how it is affected by the work function of the metal gate electrodes. Physical models used for simulations were corroborated by experimental results from SiO2 and HfO2 gate dielectrics with TaN electrodes. In bulk CMOS results show that, at the same capacitance equivalent oxide thickness (CET) at inversion, replacing a poly-Si gate by metal reduces: the gate leakage appreciably by one to two orders of magnitude due to the elimination of polysilicon gate depletion. It is also found that the work function ф β of a metal! gate affects tunneling characteristics in MOSFETS. It is particularly significant when the transistor is biased at accumulation. Specifically, the increase of ф β reduces the gate-to-channel tunneling in off-biased n-FET and the use of a metal gate with midgap ф β results in a significant reduction of gate to source/drain extension (SDE) tunneling in both n- and p-FETs. Compared to bulk YET, double gate (DG); VET1 has much lower off-state leakage due to the smaller gate to SDE tunneling. This reduction in off-state leakage can be as much as three orders of magnitude when high-κ gate dielectric is used. Finally, the benefits of employing metal gate DG structure in future CMOS scaling are discussed. [ABSTRACT FROM AUTHOR]

Features a study which presented the effects of Fowler-Nordheim and hot-carrier stress in the direct-current current voltage (DCIV) measurements. Principle of the DCIV method for obtaining interface trap density; Fabrication of LDD p metal-oxide semiconductor field-electric transistors with phosphorus-doped poly gates through commercial process; Conclusion.

In this letter, we report for the first time the impact of gate dielectric geometry on gate tunneling in a cylindrical-gate (CG) nanowire (NW) transistor. An analytical 2-D gate tunneling model is developed and used to assess quantitatively the tunneling probability in the CG NW transistor. A reduction in gate tunneling probability is predicted in the CG NW transistor compared with a planar-gate (PG) transistor with the same dielectric thickness. This effect can be very significant when the dielectric curvature is large as in practical NW devices. A high- k gate dielectric is more effective in suppressing the gate tunneling in CG transistors than in PG transistors. [ABSTRACT FROM AUTHOR]