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Multi-turn dialogue is challenging because semantic information is not only contained in the current utterance, but also in the dialogue context. In fact, understanding multiturn dialogue is a dynamic process. With the increase of dialogue turn, users' understanding is also changing. In this case, we propose a network based on utterance hidden state transfer for task-oriented dialogue (USET). In our model, we first extract the hidden state of previous utterance as the previous comprehension. Then, this comprehension is passed to the next turn. We take the comprehension as a prior knowledge to understand the semantic information in the dialogue context. Finally, we put the previous comprehension and current utterance together to understand current utterance. In order to realize the transfer of comprehension in dialogue, we propose a continuous sample training method: CST, which takes a multi-turn dialogue as a whole to understand. All the sentences in a dialogue are put into a batch for training. Our method makes use of previous comprehension and achieves the information exchange among dialogue. Experimental results on Stanford Multi-Domain dataset demonstrate that our model is superior to existing models. Code is available at https://github.com/season1blue/USET

Collecting a large amount of labeled data is crutial for training deep neural network, which is a limitation for medical image classification because it necessarily involves expert knowledge. To mitigate this problem of insufficient labeled medical data, in this work, we propose a novel semi-supervised framework for medical image classification. For unlabeled data, we apply the consistency-based strategy to produce high-quality pseudo label, which encourages model to output the same predictions under different perturbations. In addition, we present a novel mixed sample data augmentation CamMix to effectively exploit the relation between samples, mixing pairs of input data and labels according to the class activation map mask. We have evaluated our proposed method on two public medical image datasets, interstitial lung disease dataset and ISIC 2018 skin lesion analysis dataset. The results demonstrate superior performance of our method over other existing methods on the two datasets. Meanwhile, our proposed CamMix performs better than the current mixed sample data augmentation methods.

In the intelligent IoT edge devices, power consumption is increasing due to the deployment of high-precision algorithms, which greatly limits the working time of the devices. The power of A/D conversion and data transmission has become the bottleneck of traditional visual system. In this paper, a new sensing-with-computing (Senputing) architecture is proposed to reduce this power bottleneck by combining imaging and BNN 1st-layer feature map computation. This Senputing architecture has two working modes, Normal-Sensor mode and Direct-Photocurrent-Computation mode with different resolutions (128×128 and 32×32). An ultra-low-power CMOS image sensor (CIS) chip with Senputing architecture is proposed to verify the feasibility. Our CIS chip is simulated with 180nm CMOS technology, the power of feature map computation is 5.9μW, and the frame rate is 208fps. The computation efficiency reaches to 8.23TOPs/W, which is 10.1 x higher than previous works.

A new robust strap-down inertial navigation system (SINS) and Doppler velocity log (DVL) integrated navigation algorithm are proposed in this paper with a focus on suppressing the process uncertainty and measurement outliers induced by severe manoeuvering. In the proposed algorithm, the one-step predicted probability density function is modeled as Student's t-distribution to deal with the heavy-tailed process noise, and hierarchical Gaussian state-space model for SINS/DVL integrated navigation algorithm is constructed. To detect and eliminate the measurement outliers, each measurement is marked by a binary indicator variable modeled as a beta-Bernoulli distribution. The variational Bayesian approach is used to jointly estimate state vector, auxiliary random variable, scale matrix, Bernoulli variable, and beta variable. The experimental results illustrate that the proposed algorithm has better robustness and navigation accuracy to deal with process uncertainty and measurement outliers than existing state-of-the-art algorithms.

Stacked Ge nanosheets (NSs) GAA FET CMOS inverters are demonstrated for the first time. In this work, for formation of well-defined stacked Ge NSs, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material for the following better selective etching between Ge/Si. In order to avoid island growth, Ge/Si multilayers must be grown at a low temperature. For selective etching, we found that, at a proper temperature, the Si layers can be easily etched away over Ge layers with good selectivity by TMAH solution. Additionally we found the dislocations in suspended Ge sheets are more easily to be removed than the case that Ge layers are still tied with Si layers. Finally, a functional Ge NSs GAAFET CMOS inverter with maximum voltage gain of 25V/V was demonstrated.

Smart transportation is a major aspect of smart city which aims at improving traffic operation level, dispatching and overall supervision. How to alleviate traffic congestion, which is particular severe in large cities, is a cardinal facet of transportation. Special vehicles refer to vehicles dedicated to special tasks, like police cars, ambulances and are very dependent on road patency. It could be a life matter if a special vehicle on a mission encounters traffic congestion. Most of the existing traffic control systems do not target on special vehicles. Existing traffic control systems for special vehicle have weaknesses like unable to precisely detect the condition of special vehicles. In this paper, we proposed a traffic light control system based on dual mode identification, which aims at providing priority for special vehicles in a crowded city. By using dual mode identification, the condition of vehicles can be more precisely defined and accuracy performance is improved. In addition, we applied control and compensate time for the intersection to prioritize special vehicles and restore original state. In the system simulation and evaluation results, the proposed traffic light control system achieves 29% of time saving for special vehicles to get through an intersection and the intersection requires 4 cycles to fully recuperate to original condition.

In this paper, a compact microstrip duplexer with relatively close channels is proposed. The ring resonator and the orthogonal-feed are directly connected to form a band elimination filter. The band elimination filter is loaded with branches to realize the band-pass filter. The design of the duplexer in the article composed of two such band-pass filters. The design method of the duplexer is introduced in detail, and verified by the experimental results of the manufactured duplexer. The central frequency of the bandpass channels is 1.45Ghz and 1.75Ghz respectively. The measurement results show that the two channels of the duplexers are close to each other, with low insertion loss and high out-of-band rejection, which are in good agreement with the simulation results.

In this paper, a monolithic microwave integrated circuit (MMIC) power amplifier with a single-chip MMIC and a single-path output matching network is demonstrated by adopting an on-chip linearizer. The linearizer is composed of the base-emitter diode of an active bias transistor and a capacitor to provide an RF short at the base node of the active bias transistor. The saturated output power of the power amplifier (PA) is about 34 dBm at 1 GHz. The PA achieves 1 dB compression point of output power of 31.8 dBm at 25°C and an Output 3rd order in-terceot point of about 45.5 dBm.

Memory wall has been a major bottleneck that restrains the speed and power consumption of processors in the Von Neumann architecture. Computing-in-memory (CIM) was proposed as a promising method to tackle the memory wall by implementing computing in memory instead of fetching the value from memory to the processor. Based on the standard 6T -SRAM, this paper proposes a compact CIM (C2IM) unit of 10 transistors. This C2imunit is capable to not only implement the complete function of SRAM, but also realize the multiplication between the input, which is copied into the unit through the current mirror, and the value stored in the SRAM. Current-mode circuits are adopted in this unit so that it can implement higher energy efficient multiply-accumulate (MAC) operation with simpler control timing and transistor cost. Based on TSMC 65nm CMOS lower power process, the proposed unit can achieve 166.67 TOPS/W energy efficiency under 200MHz clock frequency.

Ultra-high frequency (UHF) partial discharge detection systems have broad application prospect in fault diagnosis of GIS, transformers and cables. Sensitivity is an important parameter of UHF partial discharge detection systems. Standard device-monoconical transverse electromagnetic cell (TEM) cell is established for sensitivity calibration with standard calculated electric field. The sensitivity of six UHF partial discharge detection systems are calibrated in labs, whose results is in accordance with the field test verification. The results indicate that standard device-monoconical TEM cell is a possible solution for the calibration of the sensitivity of UHF partial discharge detection systems.

In this paper, we fabricated TiN/HfO 2 -based gate stacks on epi- Si 0.5 Ge 0.5 substrates with remarkably low interface trap density (Dit) by optimizing the temperature and pressure in the annealing ambient. We found that oxygen in ambient play a subtle role in the resultant properties of the gate stack. During annealing, insufficient oxygen supply to the stack cannot effectively repair the slow oxide traps, while too much oxygen will cause excess SiGe surface oxidation and lead to higher Dit. For the first time, the impact of diffused oxygen during thermal processing on the electrical properties of the TiN/HfO 2 /IL/SiGe gate stack is systematically investigated.

Horizontally stacked Ge nanosheet GAA FETs are demonstrated, although Si, SiGe and GeSn stacked nanosheet FETs have been reported. The problem for formation of stacked pure-Ge nanostructures is that the Ge material is weaker than other IV group materials, and securing Ge material by selective etching away other IV group materials is difficult. In this work, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material, because the large difference of material properties between Ge/Si is beneficial to the following selective etching process. In order to avoid island growth, Ge/Si multilayers must be grown at a low temperature. For selective etching, we found that, at a proper temperature and with assistance of megasonic agitation, the Si layers can be easily etched away over Ge layers with good selectivity by TMAH solution. Additionally we found the dislocations in suspended Ge sheets are more easily to remove than the case that Ge layers are still tied with Si layers. Finally, the devices with gate length of 80nm were fabricated, and current of over $1650\mu A/\mu m$ (per width of channel footprint) was achieved.

Speech feature extraction is an indispensable module in the whole speech recognition process. Especially in the energy-constrained internet of things nodes, low-power feature extraction greatly improves the working time of the system. This paper optimizes a complete energy-efficient speech feature extraction architecture in the mixed-signal domain for speech recognition. The speech feature extraction architecture extracts acoustic features in the mixed-signal domain, which significantly reduces the cost of Analog-to-Digital Converter (ADC) and computational complexity. Moreover, the noise robustness of the mixed-signal MFCC feature has been investigated to adapt to the real scene. In order to evaluate the performance of the proposed optimized architecture, we fabricate a chip about the proposed feature extraction architecture in 180nm CMOS process, the post-simulation results show that the core of mixed-signal MFCC feature extraction achieves 70% power saving and enhanced noise robustness than state of the art.

Deep neural networks have achieved highly competitive performance in multiple tasks in recent years. However, discovering state-of-the-art neural network architectures requires substantial effort from human experts. To speed up the process, neural architecture search (NAS) has been proposed to search promising architectures automatically. Nevertheless, the search process of NAS is computing-expensive and time-consuming, which even costs thousands of GPU days. In this paper, to solve the bottleneck, we apply the randomness-enhanced tabu algorithm as a controller to sample candidate architectures, which balances the global exploration and local exploitation for the architectural solutions. In addition, more aggressive weight-sharing strategy is introduced into our method, which significantly reduces the overhead of evaluating sampled architectures. Our approach discovers the recurrent neural architecture within 0.78 GPU hour, which is 15.3x more efficient than ENAS [1] in terms of search time, and the architecture we discovered achieves the test perplexity of 56.1 on Penn Tree Bank (PTB) dataset, which is lower than ENAS by 2.2. In addition, we further demonstrate the usefulness of the learned architecture by transferring it to wiki-text-2 (WT2) dataset well. Moreover, the extended experiments on the WT2 dataset also show promising results.

In the past few years, the demand for intelligence of IoT front-end devices has dramatically increased. However, such devices face challenges of limited on-chip resources and strict power or energy constraints. Recent progress in binarized neural networks has provided promising solutions for front-end processing system to conduct simple detection and classification tasks by making trade-offs between the processing quality and the computation complexity. In this paper, we propose a mixed-signal perception chip, in which an ADC-free 32x32 image sensor and a BNN processing array are directly integrated with a 180nm standard CMOS process. Taking advantage of the ADC-free processing architecture, the whole processing system only consumes 1.8mW power, while providing up to 545.4 GOPS/W energy efficiency. The implementation performance and energy efficiency are comparable with the state-of-the-art designs in much more advanced CMOS technologies. This work provides a promising alternative for low-power IoT intelligent applications.

The underwater environment is complex and variable, and other navigation methods that can assist the inertial navigation for positioning are often only effective in specific areas. In the cross-region, the seamless connection between different navigation methods and the plug-and-play between sensors are particularly important. Aiming at this problem, a new underwater ASPN algorithm based on factor graph is proposed in this paper. In the graph optimization, the preintegration of IMU is applied to realize the plug-and-play between different sensors. Finally, the inertial navigation and long baseline underwater positioning are taken as examples to simulate the feasibility of the proposed algorithm.

Horizontally five stacked pure-Ge nanosheets (NSs) GAA FETs are demonstrated. In this device process, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material, because the large difference of material properties between Ge/Si is beneficial to the selective etching process. In order to avoid island growth, the flat Ge/Si multilayers are grown at a low temperature. Due to the excellent selective etching, the shape of Ge NSs almost keeps unchanged after etching. Additionally we found the dislocations in suspended Ge sheets are more easily to remove than the case that Ge layers are still tied with Si layers. Since the stacked NSs channels is tall and the pitch between channels is short, the conventional wrap-around contact (WAC) is not applicable. Here for the first time we propose the conformal monolayer doping (MLD) method for source/drain doping of tall NSs FETs.

In this paper, hybrid multi-frame image super-resolution (SR) algorithm is proposed. This method combines the concepts of both multi-frame and single-frame SR to generate a high-resolution (HR) image. Specifically, the multi-frame SR stage is executed through the hierarchical iterative sub-pixel registration method and multi-channel memristive pulse coupled neural network (MPCNN) based image fusion method. And the single-frame SR stage using the sparse coding based method is performed for improving the image quality of the HR image. Finally, a series of contrast experiments and the relevant subjective/objective analysis jointly illustrate the effectiveness and superiority of the entire scheme.

To solve the optimization problem of cloud manufacturing resources scheduling, the optimal model, which based on the object of accomplishing the task at the lowest cost and shortest time, is built. A new algorithm of cloud manufacturing resources scheduling, which combined the bat algorithm with cellular automata, is proposed. The ROV coding technique was applied to the bat algorithm for coding and decoding of the individual position vector and the velocity vector, So the scheduling problem with continuous is converted into discrete problem. The objective function is solved by using the bat algorithm, and the optimal solution is obtained. The final results proves the effectiveness and feasibility of the algorithm.