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This work demonstrates the high-frequency and high-power performance capacity of GaN high electron mobility transistors (HEMTs) on Si substrates. Using a T-gate and n++-GaN source/drain contacts, the InAlN/GaN HEMT with a gate length of 55 nm and a source-drain spacing of 175 nm shows a maximum drain current ID,MAX of 2.8 A/mm and a peak transconductance gm of 0.66 S/mm. The same HEMT exhibits a forward-current-gain cutoff frequency fT of 250 GHz and a maximum frequency of oscillation fMAX of 204 GHz. The ID,MAX, peak gm and fT-fMAX product are among the best reported for GaN HEMTs on Si, which are very close to the state-of-the-art depletion-mode GaN HEMTs on SiC without a back barrier. Given the low cost of Si and the high compatibility with CMOS circuits, GaN HEMTs on Si prove to be particularly attractive for cost-sensitive applications. [ABSTRACT FROM AUTHOR]

A four-bit four-wire four-level (4B4W4L) single-ended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of $\sim 10$ dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential sensing without a reference voltage at RX, to maintain the pin efficiency of 100%, and also to reduce EMI by setting the sum of currents through the four wires to be zero. A capacitive pre-emphasis scheme modified for four-level signaling is also used at TX to compensate for inter-symbol interference. The transmitted four-level signals are recovered by six differential comparators with an offset compensation and a decoder at RX. The proposed transceiver chip fabricated in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2 inch FR4 channel at 8 Gb/s. [ABSTRACT FROM PUBLISHER]

A switched-diode termination (SDT) is proposed to implement a low-power transceiver circuit for on-chip single-ended signaling through a through-silicon via (TSV). The channel signal swing is limited to 40 mV by the SDT to reduce the transmitter (TX) power. An inverter-cascade amplifier is used to reduce the receiver (RX) power. The SDT consists of an nMOS diode and a pMOS diode, which are connected in a series between power rails through the RX input node. Only one of these two diodes is switched on depending on the RX output data, which eliminates the short-circuit current of the center-tap resistor termination. Inverter feedback is applied to the cascade amplifier of the RX to increase the bandwidth from 0.9 to 5.0 GHz. The transceiver in the 65-nm CMOS process combined with an emulated five-stack TSV on the same chip works at 8 Gb/s with 149 fJ/b/pF and a 1.2-V supply. [ABSTRACT FROM AUTHOR]

A low-energy single-ended duobinary transceiver is proposed for the point-to-point DRAM interface with an energy efficiency of 0.56 pJ/bit at 7 Gb/s. The transmitter power is reduced by decreasing the signal swing of transmission channel to 80 mV and replacing the multiplexer and the binary output driver in the transmitter by a duobinary output driver. A trans-impedance amplifier (TIA) is used at the receiver end of transmission channel. The TIA works as a receiver termination and also amplifies the input signal for subsequent processing. Analysis of the feedback loop delay and the nonlinearity of the TIA shows that they do not impose serious problems. The TIA output signal is applied to a duobinary-to-NRZ converter, which is implemented by using a direct feedback 1-tap DFE circuit with a tap-coefficient of 1.0. The reference voltage of the duobinary-to-NRZ converter is calibrated automatically to enable a small-swing signaling. The proposed transceiver chip in a 65 nm CMOS process works at 4.5 Gb/s with a 3″ FR4 microstrip line, and at 7 Gb/s with a 0.6″ FR4. [ABSTRACT FROM AUTHOR]

A single-ended transmitter (Tx) is proposed to compensate for the crosstalk-induced jitter (CIJ) of coupled microstrip lines by subtracting a mimicked crosstalk waveform from data signal at Tx during the data transition time, depending on the data transition of an adjacent line. Since the CIJ component is proportional to the time derivative of data signal, the mimicked crosstalk waveform subtracted at Tx cancels the CIJ at receiver (Rx) for the linearly changing data signal with time. As a by-product, this scheme reduces ISI at Rx. The Tx chip in a 0.13-\mum CMOS process reduces the total Rx jitter by 96 ps (69%) at 7.2 Gbps (4-in channels) and by 120 ps (72%) at 6 Gbps (8-in channels). [ABSTRACT FROM AUTHOR]

A 2-Gb/s point-to-point intrapanel interface for thin-film-transistor liquid crystal display (TFT-LCD) is proposed by using only clock and data lines. Extra control lines are eliminated by sending the VSYNC code through the clock line at the start of the VBLANK time period and by sending the control commands through the data line at the end of the VBLANK time period. To reduce electromagnetic interference, the slew rate of the clock driver is reduced, and the frequency of clock signals is set to the subpixel (R/G/B) frequency (1/10 of the data rate). The clock line is cascaded between two adjacent receiver (RX) chips for a point-to-point interface. To generate an internal clock synchronized (deskewed) to the subpixel (R/G/B) boundary of incoming data at each RX, a single all-digital delay-locked loop (DLL) circuit is proposed to perform the combined operation of a DLL and a phase interpolator. This deskew operation is performed during the VBLANK period with periodic preamble data input (‘1111100000’). At the RX, a multiphase DLL follows the deskew DLL to generate 20-phase clocks for data sampling. 2-Gb/s data are transmitted through a series connection of a 100-cm-long flat flexible cable and a 50-cm-long FR4 microstrip line with a bit error rate less than 1e–12. The image test was successfully performed with a 42-in full-high definition 120-Hz LCD panel at 1.5 Gbps. The area and power consumption of RX chip is 0.35 \mm^2 and 52.4 mW at 2 Gbps with a 0.18- \mu\m complementary metal–oxide–semiconductor process and a 1.8-V supply. [ABSTRACT FROM PUBLISHER]