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Increased space system performance is enabled by access to high-performance, low-power radiation-hardened micro-electronic components. While high performance can be achieved using commercial CMOS foundries, it is necessary to mitigate radiation effects. This paper describes approaches to fabricating radiation-hardened components at commercial CMOS foundries by the application of novel design techniques at the transistor level, the cell level, and at the system level. This approach is referred to as hardness-by-design. In addition, trends in the intrinsic radiation hardness of commercial CMOS processes will be discussed. [ABSTRACT FROM AUTHOR]

Radiation-induced edge-leakage current in minimum geometry n-channel MOSFETs from five submicron technologies is examined as a function of dose rate. Under worst-case bias, degradation of transistors from the TSMC 0.35-, 0.25-, and 0.18-μm processes is more severe following low-dose-rate irradiation than following high-dose-rate irradiation and anneal. The leakage current anneals with an activation energy of ∼1.0 eV, which suggests that charge trapping in the field oxide is associated with shallow defects such as E'δ centers. A comparison of the device response to a first-order kinetics model for hole trapping and annealing indicates that the enhanced degradation results from slower annealing rates following low-dose-rate irradiation. These results suggest that space charge in the field oxide may contribute to the dose rate sensitivity by altering the spatial distribution of trapped holes. In contrast to the response of the TSMC parts, high-dose-rate irradiation and anneal bounds low-dose-rate degradation of transistors from the HP 0.50- and 0.35-μm processes. These results imply that existing qualification approaches based on high-dose-rate irradiation and anneal may not be conservative for the hardness assurance testing of some advanced CMOS devices. [ABSTRACT FROM AUTHOR]

The use of annular MOSFET design, which has demonstrated total-dose radiation immunity in CMOS circuits, can improve the hot-carrier reliability of CMOS circuits by reducing the drain electric field compared to conventionally designed MOSFETs. A theoretical analysis of the annular n-MOSFET in saturation verifies the reduction of the drain electric field in properly designed MOSFETs. Hot-carrier data for an enclosed 0.25-μm n-MOSFET demonstrate an improvement in hot-carrier lifetime by more than 3x compared to a conventional device in the same technology. [ABSTRACT FROM AUTHOR]

Results are presented on technique using displacement damage from energetic ions to suppress single event latchup in commercial off-the-shelf (COTS) CMOS integrated circuits. Ions implanted through the back of a thinned chip degrade the parasitic bipolar transistors causing latchup without degrading chip functionality or the parametrics of the chip. [ABSTRACT FROM AUTHOR]

Presents a study that examined the thresholds for laser-induced latchup on epitaxial complementary metal oxide semiconductors test structures for 600 nanometer and 815 nanometer excitation. Analysis of different latchup triggering mechanisms; Assessment of heavy ion measurements; Details of the test structure characterization.

Presents a study that examined the geometric component of charge pumping current in n-channel metal-oxide-silicon field effect transistors. Investigation of irradiation and electrical characterization; Analysis of oxide-trapped charge dependence; Assessment of the substrate hot-electron injection.

Deals with a study which demonstrated radiation-hard applications specific integrated circuit design enabled by the trend in commercial microelectronics toward increased radiation hardness. Description of traditional method of achieving radiation hardness; Materials and methodology used; Results and discussion.