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Fault classification in power transmission lines is important in distance relaying for identifying the accurate phases implicated in the fault occurrence. Generally, the accuracy of fault classification algorithms is evaluated by simulation data, which shows quite different characteristics from real fault data. Also, most of the previous works on fault classification used a single-stage method such as a rule-based algorithm or machine learning-based algorithm. Because of the diverse characteristics of real fault data, the performance of the single-stage method is limited. To address these issues, this paper proposes a novel two-stage algorithm that combines the strengths of rule-based and machine-learning algorithms to improve the accuracy of real fault data. A case study using real fault data shows that the proposed two-stage algorithm outperforms other conventional single-stage algorithms.

The development of combat systems requires validation and evaluation (V&E) at all phases of the V process. In the V process, two types of data should be obtained for the V&E activities: simulation data for the requirement analysis phase and real-world data for the evaluation phases. In this paper, we propose a data-based V&E system (DVES) that can be utilized for all phases of the V process. The proposed system consists of a data collection module and a V&E module. The data collection module is a file system for collecting two-typed data and contains a data distribution service interface to interoperate with real systems. The V&E module loads the data and performs practical V&E functions such as validating a submarine’s tactical behaviors or evaluating detection errors of a radar system. We conducted experiments in a submarine’s hardware-in-the-loop simulation environment to test the proposed system. The experimental results showed that the proposed system could successfully validate optimized engagement simulation tactics. In addition, we could derive radar performance evaluations and validate torpedo launch procedures. We expect the proposed work to be significant in providing a system for integrated V&E during the development phase of combat systems.

In this paper, we propose a novel switching modulation scheme for three-phase four-leg inverters that enables the separation of the fault points occurring in AC distribution networks. The proposed method is aimed at continuously supplying normal voltage to the remaining healthy phases while applying zero voltage to any faulty phase when a single line-to-ground (SLG) fault occurs in the distribution network. This modulation scheme allows isolation without physically blocking the point of failure. This can prevent unnecessary continuous outages in the AC distribution network. To this end, we propose a novel coordinate transformation method to extract accurate values for the magnitude of unbalanced three-phase voltages. A novel space vector pulse-width modulation (SVPWM) method for switching schemes that are used under fault conditions is also presented. The proposed coordinate transformation considers a plane lying in a three-dimensional (3-D) space that describes the rotation of a three-phase voltage vector. This transformation converts a physical quantity that rotates in 3-D space into a value that moves in two-dimensional (2-D) space. Subsequently, the use of synchronous reference frame (SRF) transformation enables the detection and control of the voltage magnitude in case of an SLG fault. Additionally, switching vectors are selected to apply zero voltage to the faulty phase by analyzing the switching vector diagram of a four-leg inverter. Mathematical analyses conducted for the entire process are detailed herein. Further, the experimental results of four-leg inverters designed for the 10 kW class verify the proposed strategies.

We propose a vertical linear motor (VLM) for semiconductor manufacturing equipment that compensates for the weight of the moving part by using the balance of magnetic and elastic forces. The developed VLM achieves zero stiffness with a constant upward force over a working range. The magnetic circuit of the VLM is designed to provide a linear negative stiffness over a ±2 mm stroke, with an upward force of 14 N at a 0 mm stroke. The negative stiffness is compensated for by the positive stiffness of elastic component-like springs. The upward force is then constant over the working range and corresponds to the weight of the moving part. The proposed VLM is designed to minimize the coupling effects of stiffness and gravity compensation forces by using magnetic flux saturation and magnetic flux path design. We investigate the effects of each design parameter on VLM operation through finite element analysis. Finally, the simulated forces in the proposed VLM are experimentally verified, indicating a linear negative stiffness of approximately −13.5 N/mm and a gravity compensation force of 14.9 N.

Graph neural networks (GNNs) have demonstrated superior performance in various tasks on graphs. However, existing GNNs often suffer from weak-generalization due to sparsely labeled datasets. Here we propose a novel framework that learns to augment the input features using topological information and automatically controls the strength of augmentation. Our framework learns the augmentor to minimize GNNs’ loss on unseen labeled data while maximizing the consistency of GNNs’ predictions on unlabeled data. This can be formulated as a meta-learning problem and our framework alternately optimizes the augmentor and GNNs for a target task. Our extensive experiments demonstrate that the proposed framework is applicable to any GNNs and significantly improves the performance of graph neural networks on node classification. In particular, our method provides 5.78% improvement with Graph convolutional network (GCN) on average across five benchmark datasets.

This paper discusses two modeling and simulation (M&S) issues for defense cyber-physical systems (CPSs): 1) model-driven development via model interoperation and 2) simulation analysis between interoperated models. To clearly describe the network capabilities between the CPSs within network-centric warfare (NCW), we first modeled communication factors separately from the overall CPSs. The CPS models and the network model were considered discrete event systems, which were realized with DEVSim++ and ns-3, respectively. For the simulation of the two types of models, we interoperated them with high-level architecture-based middleware to preserve the independence of each one. The goal for NCW analysis is to find a balance between the computational, physical, and communication factors of the defense CPSs to achieve their missions within a networked environment. In the case study of network-centric ground warfare, the CPS models generate mission effectiveness to be analyzed according to realistic network conditions; and at the same time, the network model enables the analysis of the network performance given validated combat scenarios. We expect this paper will help simulation experts interactively analyze computational and physical capabilities of the CPSs as well as communication effects between the CPSs.

System of systems (SoS) engineering ensures that subsystems successfully interoperate with one another via a physical network along with the designed interface specifications. The twofold challenge that motivated the authors is regarding the achievement of the interoperability for an SoS-based combat system as follows: 1) the validation of the interface specifications against the specified requirements at the system-design phase and 2) the verification of the subsystems against the interface specifications at the system-integration phase. To this end, an interoperability validation and verification toolset (IVVT) consisting of the following three components was developed: signal distributor, message collector, and message analyzer. The signal distributor captures the signal data in the middle of the existing communication interfaces, the message collector stores the signals in the form of distinguishable messages, and the message analyzer evaluates the messages by comparing the designed interface specifications that cover the communication syntax and semantics. For the experimentations, the developed IVVT was utilized for the combat systems of real submarines that have been domestically targeted for a renovation project. The objective of the experiments is the validation of the overall designed interface specifications before the development of the subsystems. The empirical results show that 12 fault cases were found in the specifications, some of which are extremely critical; therefore, a preferential validation of the specifications could prevent the incompatibilities between the subsystems during the combat system integration. In a future work, the authors will employ the IVVT for a verification of the developed subsystems to be integrated depending on the validity of the interface specifications.

The conventional range resolution improvement (RRI) technique combines two spectra of two received pulses with linear frequency modulation (LFM) in the range-frequency domain. However, its application to frequency-modulation continuous-wave (FMCW) radar is not straightforward. This study proposes an RRI method for two FMCW radars using cross-track interferometry (CTI), which are placed at different positions along the cross-track axis. Through the combination of the deramped signals of the two FMCW radars with the RRI, an improved high-resolution range profile (HRRP) was obtained. Furthermore, the simulation and experimental results validated the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This brief presents a 32-Gb/s PAM4-Binary bridge for the next-generation memory testing. The bridge incorporates all the required functions to evaluate a high-speed PAM4 memory using a low-speed NRZ tester. The low-speed data transmitted from the NRZ tester to the bridge are converted into high-speed PAM4 data through half-rate clock control and forwarded to the memory, and vice-versa. The ground-terminated PAM4 driver provides the single-ended output by controlling the output current with a 2-tap feed-forward equalizer, achieving a ratio level mismatch (RLM) of 0.95. To minimize the offset at the PAM4 receiver, the offset cancellation circuit with an offset of 2.76mV consisting of a CTLE and sampling latches is employed, and the horizontal margin of the received PAM4 signal is 50% for BER ${ < } 10^{-9}$. An all-digital PLL integrated in the bridge doubles the 4-GHz WCK used as forwarded clock for the graphic memory. The count-based PAM4 eye-opening monitor is also proposed to find the optimal codes for the maximum eye opening using the PRBS7 data sequence. The bridge fabricated in the 40-nm CMOS technology occupies an active area of 1.6mm2 and dissipates 132mW. [ABSTRACT FROM AUTHOR]