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In this paper, current-voltage-temperature (I-V-T) characteristics of vertical diodes realized by different selective epitaxial growth techniques have been investigated. Diodes by the batch-type cyclic SEG process at low temperature have shown eligible performances for vertical switches, including ideality factor of 1.08, off-current of 1.0×10−12 A and on/off-ratio of 2.4×108. The optimization of crystallographic defects and series resistance is expected to be the most critical for the performances of vertical diodes for next generation memories.

In this article, we report improved results of 4-bit double SONOS memories (DSMs) with 4-storage nodes through the optimization of ONO layer thicknesses for front and back sides. They show more balanced characteristics between the front and back channels, higher VTH shifts above 2.4V, larger read margins above 1.6V, better endurance, and longer retention time than our previous results. In addition, we also propose and demonstrate a highly scaled 4-bit DSM using multi-level technology. The VTH shifts above 4V splitting into 4 levels without noticeable interferences are achieved. Each nodes show clear 4 levels with good retention

Abnormal gate oxide thickening at active edge (GOTAE) has been investigated in dynamic random access memories (DRAMs) with SiN-lineared shallow trench isolation (STI). 1% of gaseous HCl, which is added during dry oxidation, plays a major role in inducing abnormal GOTAE by the mechanical interaction with thin SiN layers in STI. Other structural parameters, such as the thickness of trench sidewall oxide, liner SiN and sacrificial oxide, are believed to influence the amount of oxide thickening. In order to avoid abnormal GOTAE, wet oxidation is introduced and shown to be effective in suppressing it. Electrical properties, which are susceptible to the extent of GOTAE, are also presented in this paper.

P+ to p+ isolation degradation that causes DRAM standby current failure under burn-in mode operation is investigated. Although the isolation of the test devices dose not show any degradation or weakness in conventional electrical characterization, it is found that the degradation can be observed by a carrier injection method. Using the simple carrier injection method to simulate the real operating condition of a DRAM chip, a potential problem of the isolation degradation can be easily found, which cannot be screened by conventional electrical measurement.