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Scaled IGBT for 5V gate voltage operation is a key technology to reduce the V CEsat and the driver power consumption. In this paper, we experimentally demonstrate a self-turn-on free 1200V scaled CSTBT™ driven by 5V gate voltage. By using narrow mesa and fine n+-emitter pattern, low V CEsat and wide SOA was obtained. Also, high self-turn-on immunity even without negative gate bias was achieved owing to low C res /C ies ratio.

This paper discusses the near-field measurement results of deployable seven-panel parallel plate slot-array antenna system compatible with 100kg class satellite. This antenna system will be used for SAR image acquisition on-board Synspective Inc.’s first demonstration satellite Strix-Alpha, scheduled to be launched in 2020.

Transferability of self-regulated learning (SRL) knowledge is an essential feature to be developed for constructing learners' knowledge for learning SRL skills in a variety of learning situations. However, we assume two crucial difficulties: cognitive load to focus on and implicitness of SRL process. In overcoming these difficulties, this paper proposed a learning design of learning experiences in a learning environment for supporting learner’s construction of awareness of transferable SRL knowledge. The learning design clarifies the requirements of how the environment supports learning experiences with verbalization support of a mentoring task of SRL knowledge.

A 29.2Mb/mm2 ultra high density SRAM macro has been proposed using 7-nm CMOS FinFET technology. The SRAM macro has only one SRAM cell array despite of the huge array of 512 rows × 512 columns. The circuitry of dual-edge driver for such long wordline and bitline in such huge array are newly proposed. The SRAM macro using proposed circuit was designed, and a test chip was fabricated using 7-nm CMOS FinFET technology. The minimum operation voltage is improved 170 mV by the new circuits.

To learn the skill of self-regulated learning (SRL), it is important for learners to implement "metacognition of SRL" that monitors and controls SRL. However, we think there are two crucial difficulties in metacognition of SRL for non-experts of SRL skills: cognitive overload and the implicit process of metacognition of SRL. Our aim is to design a learning environment to alleviate these difficulties and motivate the metacognition of SRL. To focus learners' attention on the metacognition of SRL, we have designed a learning environment in which a learner is given an assignment to play the role of mentor to a pseudo mentee (non-human) to improve SRL. In the assignment, the learning environment provides representations about the mentee's learning situations and learner's utterances. We have designed a learning environment that allows learners to connect these representations and utterances to motivate the metacognition of SRL. This has been designed to alleviate cognitive load and promote the verbalization of SRL.

The internship is one of the crucial learning processes that provide a unique experience to combine what they learned in university courses and how to use it in the real society during their university lives as it provides the opportunity to learn through work experience offered by the external organization. Although learner can learn career skills through the internship, most learner cannot make good reflection and cannot learn how to learn from experience. We think the cause of this problem is that most learner cannot reflect their experience and cannot clear the abstract concept and apply it to the next trial. This implies that those learners can improve their learning through internship by acquiring experiential learning skills. In the internship in general, the mentor has the important education roles. One is to foster career skills learning, and the other is to promote experiential learning. However, in most case, the mentor is very good at career skill teaching, but most of the mentor is not well prepared to support experiential learning. In response to the above problems, to support learners to realized good learning, we provide a learning environment for the learner to support experiential learning. A guideline for the learner to let them aware of the critical concept of internship and experiential learning. Also, we provide a web system to practice reflective writing to understand and able to apply experiential learning concepts. In this paper, as the preliminary research to develop learning environment, the analysis of the learner learning activity of the current internship program and show the prototype of the conceptualization of the educational concepts to support the experiential learning.

Direction finding (DF) is important technology to perform wireless power transmission (WPT) for solar power satellite (SPS). For Tethered SPS, required accuracy of DF is 0.0005 degrees and high uplink power is necessary with restraint of noise level for DF system. This paper proposes use of array antennas to detect pilot signal from rectenna to SPS. Effect of wider baseline is also considered for accuracy of DF by using 1m and 5m baselines for array antennas. Error of angle of arrival (AOA) of 0.00137 degrees is obtained for 48 dB of signal to noise ratio (SNR). Estimations of uplink power are presented to achieve the needed accuracy for Tethered SPS.

Japan Space Systems (J-spacesystems) has been studying wireless power transmission (WPT) for the realization of Space Solar Power Systems(SSPS). We have been working for the essential technologies to realize SSPS. They are the improvement of total DC-RF conversion efficiency at the transmission section, RF-DC conversion efficiency at the receiving section and light weight thinner transmission panel. In order to apply microwave power technology to our daily life before space application, we have started discussion with members from Industry, Academia and Government Agencies. We believe application to the daily life can lead us to the cost effective microwave power transmission technology.

Hotel reviews posted on accommodation reservation websites are thought to be valuable information for selecting hotel accommodations and also expected to be used for marketing. Since hotel reviews are various in their expressions, it was necessary to make a thesaurus to obtain useful feature representations. Preparing a thesaurus, however, has problems such that it is laborious and requires occasional revisions. In addition, it is necessary to determine subjects of evaluation in advance and set up synonyms for them. Thus, the analysis of subjects not under consideration becomes difficult. In the present study, we first graphed impression comments using co-occurrence restrictions and dependency structures and then extracted feature representations by clustering the graphs. This enabled us to extract feature representations on evaluation from the impression comments in hotel reviews without setting up subjects of evaluation in advance and a thesaurus.

In this paper, we propose a novel backside design for Relaxed Field of Cathode (RFC) diode which realizes high avalanche stability and Undamped Inductive Switching (UIS) capability. In the case of the conventional RFC diode, wide recovery SOA is realized by forming p-layer on the backside of the edge termination area which reduces the carrier concentration at on-state and suppresses the carrier concentration on the boundary region during recovery. On the other hand, the avalanche stability at off-state of the conventional RFC diode is degraded comparing to pin diode. The failure analysis and numerical simulation taught that the avalanche stability degradation is caused by the secondary breakdown of the vertical parasitic pnp-transistor structure at the anode end. To suppress the effect of the parasitic pnp-transistor, an layer with well-adjusted width (W n ) is placed precisely under the edge of the anode area on the cathode side as the carrier sink for the electron. As a result, the new RFC diode with novel backside design obtains high avalanche stability and UIS capability without negative impact on total losses, snap-off capability and recovery SOA.

We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. The read/write assist with wordline overdrive reduces Vmln by 120 mV, achieving successful operation at below 0.5 V.

An embedded single-port SRAM with cost effective test screening circuitry is demonstrated for low-power micro controller units (MCUs). The probing test step at low-temperature (LT) of −40°C is eliminated by imitating pseudo LT conditions in the final test step where a sample is measured at room temperature (RT). Monte Carlo simulation is carried out with consideration of global and local Vt variations as well as contact soft open failure (high resistance), confirming good Vmin correlation between LT and pseudo LT conditions. Test chips with a 4-Mbit SRAM macro are designed and fabricated using 40-nm low-power CMOS technology. Measurement results show that the proposed test method can reproduce LT conditions and screen out low temperature failures with less overkill.

This paper describes thermal design and analysis of a hybrid photovoltaic module for the conversion of sunlight into microwave that is used in Tethered-Solar Power Satellite. A practical configuration of the hybrid module was designed and the relationship between module structure and temperature profile under the operation in geostationary orbit was investigated by simulation in comparison with the conventional space photovoltaic module. To obtain realistic analysis model in which practical thermal resistance is considered, thermal-vacuum test using a prototype hybrid module was conducted. The simulation result shows that contact thermal resistance of the hybrid module is small and hybrid structure can reduce the thermal stress risk.

We demonstrate 16 nm FinFET High-k/Metal-gate SRAM macros with a wordline (WL) overdriven read/write-assist circuit. Test-chip measurements confirm improved minimum operating voltage (V min ), standby leakage current, and access time compared to planar bulk CMOS. The proposed assist circuit improves V min by 50 mV and improves read-access-time by more than 1.5 times in 256-kbit SRAM macros. Read current (I read ) dependence against the fin diffusion length was observed. An extra design guard-band is needed to provide a reliable operation margin.

A 2-read/write dual-port SRAM and 1-read/1-write two-port SRAM with stable operation at temperatures of −40 to 170°C are implemented in 40 nm embedded flash CMOS technology for automotive microcontroller applications. To reduce the leakage current and to ensure the read/write operating margin at over 125°C, a new 8T SRAM bitcell with the optimized process and sizing is proposed. A test circuit for screening disturb failures for dual-port and two-port SRAMs is also proposed. Designed and fabricated test chips showed that measured V min is achieved under 0.7 V with good distribution. Results show that the proposed test circuits can screen the disturb failures effectively.

We propose a partially write-assisted two read/write dual-port (DP) SRAM in 28-nm technology. Our write-assist circuit with metal-coupled capacitance can generate negative bitline bias which is flexibly adjustable to any bit-word configurations. By effectively applying assist biases only to sub-blocks with margin-less bits, power overhead can be reduced with Vmin improved. A test chip including proposed 512-kb DP SRAM macro is designed using 28-nm HKMG technology, from which we successfully observed 1-GHz operation at 1.0 V, 190 mV Vmin improvement, and 21% power reduction compared to a conventional assist.

A 160 kb SRAM macro with stable operation under widely various temperatures of -40 to 170°C is implemented in 40 nm embedded flash CMOS technology for automotive microcontroller applications. We finely optimized MOS sizes of the 6T SRAM bitcell with process tuning to enhance the read margin and to reduce leakage power at high temperatures over 125°C. The optimized bitcell improves the static-noise-margin by 40 mV and reduces leakage power to 1/10 of the conventional value. To achieve high quality, we propose rush current suppression circuit when resuming from sleep-mode and a weak-bit test screening circuit. A designed test chip showed a measured Vmin mean of 0.65 V at 170°C and 1.86 μW/Mb (643 μW/Mb) at 25°C (170°C) with good distribution. Those are the lowest power values reported to date in published works. The estimated leakage power of a prototype MCU chip is acceptable for automotive target specifications.

Toward the orbital demonstration of a solar power satellite (SPS), a breadboard model of the SPS has been developed for preliminary experiments including wireless power transmission. The model forms a thin panel structure with a thickness of 6 cm, and the panel consists of three layers being functionally assigned to a transmission antenna, microwave amplification and control, and thermal radiation, respectively. Microwave amplified up to 160 W is emitted from a large-scale phased array antenna with 256 microstrip elements. In order to evaluate the effect of multiply arranged antennas to the emission, the measurement of the radiation pattern is conducted for different relative positions of the antenna panels. Additionally, the steering of the transmission beam is achieved as an initial demonstration for retrodirective control.

With the rapid growth in the market for mobile information terminals such as smart phones and tablets, the performance of image processing engines (e.g., operation speed, accuracy in digital images) has improved remarkably. In these processors, 2-port SRAM (2P-SRAM) macros [1], in which a read port and a write port are operated synchronously in a single clock cycle, are widely used. As shown in Fig. 13.4.1, since the 2P-SRAM is placed in front of large scale logic circuitry for image processing, a faster access time (e.g.

A novel single-switch cell voltage equalizer using voltage multipliers for series-connected supercapacitors (SCs) is proposed. Since the proposed equalizer can operate with a single switch at a fixed duty cycle when operated in discontinuous conduction mode (DCM), the circuit complexity can be reduced significantly when compared with conventional equalizers, and can also eliminate feedback control. Operation analyses are made and a dc equivalent circuit is mathematically derived to prove the voltage equalization mechanism. An experimental equalization test using the proposed equalizer operating with a fixed duty cycle was performed for series-connected SCs from an initially cell-voltage-imbalanced condition. The cell voltage imbalance was successfully eliminated with an average power conversion efficiency of 78.8%.

Although supercapacitors (SCs) offer many advantages over traditional secondary batteries, they have two major drawbacks—low specific energy and large voltage variations due to cycling. For SCs to be used as alternatives to batteries, a high efficiency power converter that can operate in a wide voltage range is required to maximize the use of the stored energies of SCs. In this paper, we propose an unregulated interface converter using cascaded switched capacitor converters (SCCs) with selectable intermediate taps for SCs in alternative battery applications. The interface converter realizes high efficiency power conversion using the cascaded SCCs, and its voltage conversion ratio is roughly regulated by selectable intermediate taps. Its operation principle and design guidelines are presented in detail. An SC module with a rated charge voltage of 60 V was cycled with a 150 W prototype whose measured peak power conversion efficiency was greater than 95%. The SC module was cycled deeply in the range of 24–60 V while the load/charger voltage was maintained between 24–33.6 V.

Supercapacitors (SCs) have potential to be good alternatives to batteries in satellite power systems because they not only have a longer life but also reduce the mass of photovoltaic arrays when they are charged using a constant-power (CP) charging scheme. In this paper, we propose singles-witch CP equalization chargers using multi-stacked buck-boost converters. In addition to the single-switch operations, the equalization chargers operating in the discontinuous conduction mode (DCM) do not require feedback control, and hence, the feedback loop can be eliminated. Operations under voltage-balanced and voltage-imbalanced conditions were mathematically generalized. An experimental charge test was performed for four SCs connected in series. The SC(s) with the lowest voltage was (were) preferentially charged by the equalization charger. The voltage imbalance was gradually eliminated, and finally, all SCs were charged to a uniform voltage level.

Since supercapacitors (SCs) have inherently long life, they can be an alternative energy storage source to traditional secondary batteries in long-life applications where the batteries are cycled with shallow depth of discharge to extend their cycle life. Cycle life performance tests were conducted under various cycling conditions in order to evaluate the feasibility of the accelerated ageing testing and cycle life prediction for SCs in alternative battery applications. The resultant capacitance retention trends could be extrapolated linearly with the square root of the number of cycles as the x-axis. Capacitance degradation ratios were mainly dependent on temperature, implying that ageing can be accelerated by elevating temperature. An ageing acceleration factor was determined from activation energies obtained from the Arrhenius equation. A cycle life prediction model for SCs was established by combining extrapolation and acceleration factor. The experimental and predicted capacitance retention trends were in good agreement, and the derived prediction model was verified to be appropriate for SCs in alternative battery applications.

Cell voltage equalizers are usually used for series-connected energy storage cells, such as lithium-ion cells and supercapacitors (SCs), to eliminate cell voltage imbalance that may cause premature deterioration and reduce the available energy of the cells. Because conventional cell voltage equalizers are based on multiple individual dc-dc converters, the number of switches, sensors, and/or transformers increases proportionally with the number of series-connected energy storage cells. As compared to conventional equalizers, a single-switch cell voltage equalizer based on multi-stacked single-ended primary inductor converters (SEPICs), which is proposed in this paper, can dramatically reduce circuit complexity because of its single-switch operation. Furthermore, feedback control can be eliminated when the equalizer is operated in discontinuous conduction mode (DCM). The fundamental operating principle and the equalization time are mathematically generalized in this paper. An experimental equalization test was performed for four series-connected SCs to demonstrate the equalization performance. The standard deviation of cell voltages decreased to approximately 1 mV at the end of the equalization process, thus verifying the proposed equalizer's performance.

We discuss dynamic stability for single-port SRAM that manifests itself in the difference between minimum operating voltage (Vmin) for longer and shorter word-line (WL) pulse width (T wl ). The most probable failure points (MPFPs) that determine Vmin for various Twl are investigated. Regarding dual-port SRAM, we identify the MPFP for the worst Vmin degraded by WL pulse skew between ports in asynchronous operation. The validity of our simulation results are verified through comparison with measured data for SRAM modules in 28 nm generation.

The cell voltage imbalance of series-connected energy storage cells such as supercapacitors (SCs) and lithium-ion cells leads to the premature degradation and a decrease in the available energy of the cells. In this study, single-switch equalization chargers using multi-stacked buck-boost converters have been proposed. The single-switch operation can dramatically reduce circuit complexity compared with that of conventional equalizers. Fundamental operating principles of both voltage-equalized and voltage-imbalanced conditions are presented. Experimental charge tests using a single ended primary inductor converter (SEPIC)-based prototype for 4-series connected SCs were performed. The experimental results demonstrated that the proposed equalization charger can charge the series-connected SCs preferentially in the order of increasing cell voltage, and all SCs were charged to a uniform voltage level. Another charge test was performed for 4-series connected SCs containing an aged cell. All the cell could be charged uniformly, regardless of individual cell capacitance.

Series-connected energy storage modules such as supercapacitors (SCs) and lithium-ion batteries cause module voltage imbalances that lead to premature deterioration of modules. Various equalization techniques have been proposed for series-connected energy storage cells/modules to alleviate such voltage imbalances. However, since the conventional topologies consist of numerous switches, sensors, inductors, or transformers, their circuit size, complexity, and costs are prone to increase in proportion to the number of series connections. This paper proposes a single-switch single-inductor equalization charger using a voltage multiplier. Because the proposed equalization charger requires only a single switch and a single inductor to operate, the circuit size and complexity can be dramatically reduced compared to that of conventional topologies. An experimental charge test was performed for series-connected SC modules with the proposed equalization charger to demonstrate its performance. Initially imbalanced voltages of the SC modules were equalized and charged to a uniform voltage level by the proposed equalization charger.

We develop electrical functional models of the space solar power system (SSPS) for the system study and the practical demonstration of the end to end capability from space to the ground. The model generates electricity by the solar array and converts the DC power into microwaves with a frequency of 5.8 GHz. The microwave beam is controlled in one dimensional direction by the pilot signal and the phase detection and control circuits. End consumer of the electricity from the space segment is demonstrated by the power utility. We will describe a design and performance of the SSPS demonstration models.

Solar Power Satellite (SPS) is an energy system which collects solar energy in space and transmits it to the ground. It has been believed as a promising infrastructure to resolve global environmental and energy problems for human beings. One of the most important technologies for the SPS is the wireless power transmission from the geostationary orbit to the ground. Microwave power transmission has been investigated and demonstrated for more than 40 years, but still requires further research regarding high-efficiency power conversion and high-accuracy beam control for SPS application. This paper introduces the concept of SPS, and presents microwave power transmission technologies necessary for SPS, their demonstration experiments both on the ground and in space in the near future, and future prospects towards commercial SPS.

DC-DC converters are commonly used as an interface between a photovoltaic (PV) module and a load because the characteristics of PV modules vary with environmental conditions. In a conventional system, all the power extracted from the PV modules is transferred through the converter with an efficiency penalty; thus, the converter must operate as efficiently as possible. This paper proposes a novel PV system in which a dc-dc converter is partially connected to series-connected PV modules. Only part of the generated power is delivered via the converter, and the rest is directly transferred to the load. Thus, the total efficiency can be higher than that of a conventional system. The operating principles of the partial converter and PV modules and an optimum design procedure are presented. Experimental tests were performed on both the conventional and proposed systems with the same buck converter to demonstrate their operating characteristics and total efficiency performance. The results showed that the proposed system could realize a higher total efficiency, and high utilization of the PV modules was also achieved by the optimum design procedure.

Conventional cell equalizers based on dc-dc converters require many switches or transformers as the number of series connections increases, raising their cost and complexity and decreasing reliability. This paper proposes a novel equalization charger that consists only of a capacitor-diode network and an ac power source. A dual capacitor-diode network configuration is also proposed to mitigate the RMS current flowing through energy storage cells during charging. The operating principle and derivation of a dc equivalent circuit are explained. Experimental charge tests were performed on series-connected supercapacitors to demonstrate the charge performance and analyze the operating waveforms.

SELENE (Selenological and Engineering Explorer) is a Japan's lunar probe which was launched and injected into the lunar polar orbit in 2007. The Main Orbiter of SELENE named Kaguya has separated the Relay Satellite: Rstar (Okina). We have executed four-way Doppler measurements which determined the orbit of Kaguya aviating above the lunar far side. The ground station up-links ranging signals, and the relay satellite transponder on Rstar (RSAT-1) relays the carrier waves to Kaguya. Then the transponder on Kaguya (RSAT-2) receives the signals and returns to Rstar, and down-linked to UDSC. Three of four receivers through four-way links acquires signals and tracks Doppler frequency shift with phased lock loops. For that purpose, the receivers should be locked sequentially under the condition of large Doppler shift due to mutual velocities of three moving bodies. The receivers were designed in consideration of the above condition and system operability. Eventually, our system has realized the first case to track two fully moving links between the lunar orbiters and carried out Doppler measurements. Results of the orbit determinations for Kaguya above the lunar far side have shown the anomaly distributions of the gravity fields which could be scarcely found by the conventional two-way RARR methods.

This paper presents a high-efficiency low-reradiation planar rectifying antenna (rectenna). The rectenna is composed of a high-gain cavity-backed circular patch antenna using novel coplanar feeding structure and a low-profile microstrip rectifying circuit. The cavity-backed antenna achieved the gain of 9.17dBi and the -20dB return loss bandwidth of approximately 1.4%. The rectifying circuit has a harmonics filter that suppresses the reradiated harmonics under -59 dBc. The RF-to-dc conversion efficiency of the rectenna element was measured as 71.4% with a 266mW input power. Over 13W DC output power was demonstrated using the 52- element triangular array.

Recently, personal digital assistants like cellular phones are shifting to the IP terminal. The encoding-decoding process utilized for transmitting over IP networks deteriorates the quality of the speech data. This deterioration causes degradation in speech recognition performance. Acoustic model adaptations could improve recognition performance. However, the current adaptation methods usually require a large amount of adaptation data. A novel adaptation method using speech synthesis based on HMM (hidden Markov model) is proposed. This method does not require speech data for adaptation because speech data is generated by speech synthesis from the acoustic model. Experimental results on G.723.1 coded speech recognition show that the proposed method improves speech recognition performance. A relative improvement in word accuracy of approximately 2% was observed.

Summary form only given. A linear dispersion relation of beam loaded slow wave structure (SWS) with finite strength guiding axial magnetic field is derived and analyzed numerically. In most theoretical analyses of high power backward wave oscillators (BWO's), the axial magnetic field to guide electron beam in the SWS has been assumed to be infinitely large. In the present paper, we derive an exact linear dispersion relation for a finite magnetic field in which space charge modes, cyclotron modes and the structure modes can interact resonantly. We consider an axisymmetric mode in an infinitely long SWS with sinusoidally corrugated metal wall in the axial direction. A solid cylindrical beam is present on the axis. The dielectric tensor in the beam region has 9 non-zero components. Coupled ordinary and extra-ordinary modes must exist to satisfy boundary conditions at the beam and metal surfaces. We assume practical size and beam parameters that have been studied in the University of Maryland and Niigata University.

Summary form only given. Protuberances (local maxima) in plasma density in the axial direction created by microwave pulses externally injected into a plasma-filled corrugated wall waveguide (slow wave structure, SWS) are observed experimentally. This is observed for moderately high microwave powers above a threshold value repeatedly under various conditions.

Summary form only given. The linear dispersion relation of the quasi-TE mode for a sinusoidally corrugated, metal wall, slow wave structure (SWS) is extended and analyzed for the case of an intense relativistic electron beam. The results of numerical analysis are compared with the experimental results. The dispersion characteristics, such as the linear growth rate and bandwidth, of the quasi-TE/sub 11/ mode are numerically analyzed and compared with those of the conventional TM/sub 01/ mode. The period, mean radius and amplitude of the SWS are 1.2 cm, 1.445 cm and 0.445 cm, respectively. Typical beam energy and current are 100 keV and 500 A, respectively. The bandwidth of the quasi-TE/sub 11/ mode is wider than that of the TM/sub 01/ mode. The oscillation frequencies of the TM/sub 01/ and quasi-TE/sub 11/ mode are 8.5 and 8.9 GHz, respectively. The temporal growth rate of the TM/sub 01/ mode is larger than that of the quasi-TE/sub 11/ mode. We have performed an X-band BWO experiment using the SWS with size parameters identical to the above numerical analysis.

The purpose of this work is the development of an estimation method of initial rotor position for surface permanent magnet (PM) synchronous motor without a position sensor. The principle of the estimation is based on the variation of the current response caused by the magnetic saturation of the stator core when the voltage vector is applied to the motor. The initial rotor position is identified by observing the maximum d-axis current caused by the magnetic saturation. This method can be performed without motor parameters and the additional hardware. A decision method of the optimal voltage vector applied to the motor is also proposed to accurately implement the estimation. Experimental results show that the initial rotor position can be estimated without rotating the rotor by using the optimal voltage vector.

The purpose of this work is development of an estimation method of initial rotor position for a surface permanent magnet synchronous motor. The principle of the estimation is based on the variation of the current response caused by the magnetic saturation of the stator core when the voltage vector is applied to the motor. This method can be performed without motor parameters and the additional hardware. The decision method of the optimum voltage vector applied to the motor is also proposed to accurately implement the estimation. Experimental results show that the initial rotor position can be estimated without rotating the rotor by using the optimum voltage vector.