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A novel method for selective deposition of metal features has been developed and evaluated for several different metallization applications in device manufacturing and advanced packaging technologies. Selectroplating® is based on a selective chemical modification (SCM) of field areas of a wafer and can be implemented for either a fill-based integration, such as Cu dual damascene, or an additive process such as plating of wide conductive lines. In either integration, the primary benefit of selective deposition is to prevent deposition of metal in areas between desired features thus eliminating the need to remove excess bulk metal in the next step.

Thin film deposition of metals is necessary in the fabrication sequence of most electronic devices, but much of the deposited metal is actually wasted in the subsequent patterning steps. In the case of copper interconnects for advanced semiconductor chips, a blanket layer of Cu is electroplated over the entire wafer to fill tiny trenches etched into a dielectric layer, then all of the metal in the field areas is removed by chemical mechanical planarization (CMP). In other devices, the conductive layer may be aluminum or some other metal, and the patterning may be based on photo and etch steps, but in nearly all cases, a large percentage of the initial metal is removed and sent down the drain or out the process gas exhaust. In recent years, packaging technologies and MEMS devices have adopted similar processes for metal layers, many of which involve even thicker layers and even more wasted metal. In all of these process sequences, substantial savings could be realized if the metal could be deposited in a selective manner and focused primarily into the features of interest rather than depositing a blanket layer.A novel method for selective deposition (Selectroplating®) has been developed and evaluated for several such metallization applications. This technology is based on a selective chemical modification (SCM) of field areas of a wafer and can be implemented for either a fill-based integration, such as Cu dual damascene, or an additive process such as plating of wide conductive lines. In either integration, the primary benefit of selective deposition is to prevent metal from being deposited in areas between desired features thus eliminating the need to remove excess bulk in the next step. Cost savings is realized in two ways: 1) less metal is consumed from the plating bath thus extending bath life and lowering the average deposition cost, and 2) substantially less bulk metal must be removed in the subtractive step which lowers the polish or etch time. This improves throughput and further decreases cost.

The applications of inertial sensors have a wide variety in terms of accuracy and costs. A new technology approach is joining higher sensor accuracy and lower production costs by using a new Interposer / sensor interconnect technology applied on 300 mm wafer diameter without changing the sensor element itself. The higher accuracy is mainly covered by a multiple point program: (1) stress less assembly due interface silicon Interposer to silicon MEMS; (2) better Signal to Noise Ratio (SNR) by polymer redistribution layer on the interposer (due to better wiring geometry and less parasitic capacities / inductivities); (3) reduction of mechanical stress by using flexible bar springs for mechanical decoupling of sensor and Interposer substrate; (4) additional stress reduction by using a polymer layer for mechanical decoupling of metal redistribution layer (RDL) and Interposer substrate. The cost efficiency even in small scale serial production based on: (1) 300 mm multi project wafer technology including warehouse ready system packaging; (2) a new MEMS contact technology, which gives technical benefit, smaller dimensions and simplifies the assembly of MEMS and ASIC (which are placed on a 2.5D-Interposer in order to enable a System In Package (SiP) as well as for higher sensor accuracy); (3) the flexible ASIC feature enables the integration of different MEMS with analogue signal output; (4) minor costs for integration of different sensors into the existing package. The heterogeneous 3D integration is a key enabler and justifies the additional process steps (mainly TSV-processing, thin wafer handling) by implementing the advantages of the polymer RDL. This integration approach results leads to improved mechanical and electrical properties. This paper will give an overview about the current achievements in the SIMEIT-project, which are predestined to improve the accuracy of different MEMS-applications with analogue signal transfer to the ASIC as well as MEMS-applications with need of stress less integration.

For considerations of stress reduction HAR-TSVs were only partially filled with copper. A comparison was made to ring shaped TSVs (i.e. copper ring with silicon core). Two approaches regarding the way of TSV implementation (before and after wafer bonding/ thinning, resp.) are discussed, concerning process ability and yield aspects. Electrical measurement yield 11 MΩ for a single TSV and 76 MΩ for a 4-point TSV-chain (incl. RDL).

The influence of CH 4 , H 2 , NH 3 and He plasma on the properties of porous low-k material is studied. It is found that the H 2 , He, NH 3 plasma can cause huge carbon depletion in the porous low-k material, and change the low-k surface from hydrophobic to hydrophilic, which will induce moisture uptake into the low-k material during the CMP process, and results in the increase of the k value and leakage current. The CH 4 plasma can make low-k material more resist against moisture uptake and keep the k value and leakage current of low-k films stable.