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A new high-gain antenna structure is proposed for mmWave 5G and potentially for B5G and 6G applications. The proposed antenna is configured by a planar segmented patch structure that has a radiator size comparable to the conventional patch but achieves more than 3 dB gain enhancement without a help of superstrate stack-up layer. The proposed planar segmented antenna (PSA) induces multiple magnetic currents through multiple segmented conductors, resulting in a strong magnetic field circulation around the conductors. Only one conductor requires an excitation port and each segmented conductor has a shorting pin to synchronize resonance currents. To verify the PSA operation, several prototypes were fabricated at 28 GHz with the identical volume of $1.213\,\,\lambda _{0} \times 1.213\,\,\lambda _{0} \times 0.113\,\,\lambda _{0}$ , including the ground plane. The maximum measured impedance bandwidth of the single PSA was 23.1%. Furthermore, the measured maximum antenna gain was 11.5 dBi, whereas the same sized reference patch antenna showed only 6.3 dBi. [ABSTRACT FROM AUTHOR]

Software-Defined Networking (SDN) has aggressively grown in data center networks, telecommunication providers, and enterprises by virtue of its programmable and extensible control plane. Also, there have been many kinds of research on the security of SDN components along with the growth of SDN. Some of them have inspected network policy inconsistency problems that can severely cause network reliability and security issues in SDN. However, they do not consider whether a single network policy itself is corrupted during processing inside and between SDN components. In this paper, we thus focus on the question of how to automatically identify cases in which the SDN stack fails to prevent policy inconsistencies from arising among those components. We then present AudiSDN, an automated fuzz-testing framework designed to formulate test cases in which policy inconsistencies can arise in OpenFlow networks, the most prevalent SDN protocol. To prove its feasibility, we applied AudiSDN to two widely used SDN controllers, Floodlight and ONOS, and uncovered three separate CVEs (Common Vulnerabilities and Exposures) that cause the network policy inconsistencies among SDN components. Furthermore, we investigate the design flaws that cause the inconsistencies in modern SDN components, suggesting specific validations to address such a serious but understudied pragmatic concern. [ABSTRACT FROM AUTHOR]

In this article, we present an effective methodology for co-design, co-analysis, and the system-level optimization of chiplet/interposer power delivery network (PDN) in 2.5-D integrated chip (IC) designs. In our methodology, we first generate a commercial-grade heterogeneous 2.5-D IC designs including full signal routing and power delivery. We then perform our PDN co-analysis in frequency and time domains on the entire PDN to evaluate various mechanisms added to our PDN designs. Based on our co-analysis results, we perform the system-level optimization on both interposer and chiplet PDNs with the stable performance of power delivery. Finally, we perform power, performance, and area (PPA) analysis and power integrity (PI) on our 2.5-D designs and discuss tradeoffs in chiplet and interposer levels due to PDN optimization. Our experiments show 27.17% improvement in the overall IR-drop in the optimized 2.5-D IC design by increasing the interposer PDN occupancy by 5.52% and inserting the additional PDN grids in chiplet designs. However, we also observe tradeoffs in terms of PPA and PI. By PDN optimization, the optimized design has an 11.6% increase of the total power, while the area of 2.5-D design remains the same. Moreover, from the perspective of PI, the tradeoffs are shown by 0.6% reduction of power efficiency, 32.6% higher output ripple, and 31.5% higher initial ringing because of an inductive behavior of interposer PDN in the optimized design. [ABSTRACT FROM AUTHOR]

There is a growing consensus that the physics-based model needs to be coupled with machine learning (ML) model relying on data or vice versa in order to fully exploit their combined strengths to address scientific or engineering problems that cannot be solved separately. We propose several methodologies of bridging technology computer-aided design (TCAD) simulation and artificial intelligence (AI) with its application to the tasks for which traditional TCAD faces challenges in terms of simulation runtime, coverage, and so on. AI-emulator that learns fine-grained information from rigorous TCAD enables simulation of process technologies and device in real-time as well as large-scale simulation such as full-pattern analysis of stress without high demand on computational resource. To accelerate atomistic molecular dynamics (MD) simulation, we have done a comparison study of descriptor-based and graph-based neural net potential, and also show their capability with large-scale and long-time simulation of silicon oxidation. Finally, we discuss the use of hybrid modeling of AI- and physics-based model for the case where physical equations are either fully or partially unknown. [ABSTRACT FROM AUTHOR]

The robustness of a network’s connectivity to other networks is often highly dependent on a few critical nodes and links that tie the network to the larger topology. The failure or degradation to such network bottlenecks can result in outages that may propagate throughout the network. Unfortunately, the presence of the bottlenecks also offers opportunities for targeted link flooding attacks (LFAs). Researchers have proposed a new and promising defense to counter LFAs, referred to as topology deception. This strategy centers on hindering the discovery of bottlenecks by presenting false trace responses to adversaries as they perform topological probing of the target network. Even though the goal of topology deception centers on obscuring critical links, node dependencies can be exploited by an adversary. However, current approaches do not consider a wide range of metrics that may reveal important and diverse aspects of network bottlenecks. Furthermore, existing approaches create a simple form of virtual topology, which is subject to relatively easy detection by the adversary, reducing its effectiveness. In this paper, we propose a comprehensive topology deception framework, which we refer to as BottleNet. Our suggested approach can analyze various network topology features both with respect to static and dynamic metrics and then use this information to identify bottlenecks, finally producing complex virtual topologies that are resilient to adversarial detection. [ABSTRACT FROM AUTHOR]

One of the favorable tools for signal integrity evaluation is eye diagram analysis. This is traditionally performed with a lengthy transient simulation, which can be prohibitively time consuming for complex high-speed channels with a low bit error rate. Methods for eye estimation exist; however, they are either only applicable to linear time-invariant systems or have lack in accuracy or efficiency. In this article, an optimization-based approach is proposed to quickly obtain the worst-case eye diagram characteristics. This approach focuses on the inter-symbol interference since its effect can span over many symbols and include crosstalk, making it challenging to model. In this article, the data patterns leading to the lowest voltage corresponding to a high symbol, the highest voltage corresponding to a low symbol, and the times of minimum and maximum level crossing points are calculated. Then, eye height, eye width, and the worst-case eye opening are estimated using these points. To reduce complexity, the proposed approach includes a mapping algorithm that exploits the Gray code. Additionally, Bayesian optimization is used because of its efficiency and good performance on non-linear and non-convex problems. Finally, the application of the proposed approach to high-speed SerDes channels, and channels in system-on-package designs is evaluated with numerical examples, where the results show its accuracy and efficiency. [ABSTRACT FROM AUTHOR]

Textual data mining of open source intelligence on the Web has become an increasingly important topic across a wide range of domains such as business, law enforcement, military, and cybersecurity. Text mining efforts utilize natural language processing to transform unstructured web content into structured forms that can drive various machine learning applications and data indexing services. For example, applications for text mining in cybersecurity have produced a range of threat intelligence services that serve the IT industry. However, a less studied problem is that of automating the identification of semantic inconsistencies among various text input sources. In this paper, we introduce GapFinder, a new inconsistency checking system for identifying semantic inconsistencies within the cybersecurity domain. Specifically, we examine the problem of identifying technical inconsistencies that arise in the functional descriptions of open source malware threat reporting information. Our evaluation, using tens of thousands of relations derived from web-based malware threat reports, demonstrates the ability of GapFinder to identify the presence of inconsistencies. [ABSTRACT FROM AUTHOR]

A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off-the-shelf intellectual properties (IPs), allows reuse of them, and enables heterogeneous integration of blocks in different technologies. In this article, we present a highly integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5-D designs. Our target design is 64-core architecture based on Reduced Instruction Set Computer (RISC)-V processor. We first chipletize each IP by adding logical protocol translators and physical interface modules. We convert a given register transfer level (RTL) for 64-core processor into chiplets, which are enhanced with our centralized network-on-chip. Next, we use our tool to obtain physical layouts, which is subsequently used to synthesize chip-to-chip I/O drivers and these chiplets are placed/routed on a silicon interposer. Our package models are used to calculate power, performance, and area (PPA) and reliability of 2.5-D design. Our design space exploration (DSE) study shows that 2.5-D integration incurs $1.29\times $ power and $2.19\times $ area overheads compared with 2-D counterpart. Moreover, we perform DSE studies for power delivery scheme and interposer technology to investigate the tradeoffs in 2.5-D integrated chip (IC) designs. [ABSTRACT FROM AUTHOR]