95 results on '"Kim, Hyesoon"'
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2. EHT-SR: An Entropy-Based Hybrid Approach for Faster Super-Resolution
3. LCP: A Low-Communication Parallelization Method for Fast Neural Network Inference for IoT
4. Spica: Exploring FPGA Optimizations to Enable an Efficient SpMV Implementation for Computations at Edge
5. Context-Aware Task Handling in Resource-Constrained Robots with Virtualization
6. Creating Robust Deep Neural Networks with Coded Distributed Computing for IoT
7. Reducing Inference Latency with Concurrent Architectures for Image Recognition at Edge
8. Traversing Large Compressed Graphs on GPUs
9. Accelerating Graphic Rendering on Programmable RISC-V GPUs
10. Maia: Matrix Inversion Acceleration Near Memory
11. RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU
12. Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads
13. FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction
14. Hardware-based Always-On Heap Memory Safety
15. MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture
16. Understanding the Software and Hardware Stacks of a General-Purpose Cognitive Drone
17. Hot Chips 2020 Posters
18. RISC-V FPGA Platform Toward ROS-Based Robotics Application
19. PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra
20. Proposing a Fast and Scalable Systolic Array for Matrix Multiplication
21. ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory
22. Tango: An Optimizing Compiler for Just-In-Time RTL Simulation
23. ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator
24. Characterizing the Deployment of Deep Neural Networks on Commercial Edge Devices
25. Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs
26. POSTER: Tango: An Optimizing Compiler for Just-In-Time RTL Simulation
27. Empirical Investigation of Stale Value Tolerance on Parallel RNN Training
28. Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware.
29. Translating CUDA to OpenCL for Hardware Generation using Neural Machine Translation
30. The 2019 Top Picks in Computer Architecture.
31. CoolPIM: Thermal-Aware Source Throttling for Efficient PIM Instruction Offloading
32. Performance Characterisation and Simulation of Intel's Integrated GPU Architecture
33. Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube
34. Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube
35. SimProf: A Sampling Framework for Data Analytic Workloads
36. ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays.
37. GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks
38. StaleLearn: Learning Acceleration with Asynchronous Synchronization Between Model Replicas on PIM.
39. BSSync: Processing Near Memory for Machine Learning Workloads with Bounded Staleness Consistency Models
40. GPUMech: GPU Performance Modeling Technique Based on Interval Analysis
41. Transparent Hardware Management of Stacked DRAM as Part of Memory
42. Design Space Exploration of Memory Model for Heterogeneous Computing
43. Harmonica: An FPGA-Based Data Parallel Soft Core
44. TBPoint: Reducing Simulation Time for Large-Scale GPGPU Kernels
45. Spare register aware prefetching for graph algorithms on GPUs
46. CHiP: A Profiler to Measure the Effect of Cache Contention on Scalability
47. OpenCL Performance Evaluation on Modern Multi Core CPUs
48. A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch
49. FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion
50. Predicting Potential Speedup of Serial Code via Lightweight Profiling and Emulations with Memory Performance Model
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