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The exponential data size growth in high-speed networks is a key motivator for nonvolatile memory development. To support this demand, higher density NAND is required: with a smaller cell size and higher interface speed. Generally, scaling down NAND technology requires addressing several common issues: 1) As the number of WL stack layers increases, the cell-string current is reduced due to the increased resistance in a cell string, 2) Deterioration of cell-to-cell interference, due to the reduction of cell pitch, 3) Support of higher IO bandwidth for faster data transfer speed [1]. Another challenge of this work was to minimize the die size because the peripheral circuit area is comparable to that of the cell array. Hence, we integrated the peripheral circuits below the cell array as introduced in [2]. Also, to cope with lower metal-contact height, a novel structure for the capacitor device was used to maximize capacitance per unit area.

Data storage is one of the hottest discussion topics in today’s connected world. The amount of data growth is expected to be exponential, while budget and space remain constricted. Since the transformation of storage device from planar NAND to 3D V-NAND [1], the areal density of semiconductor storage devices has continuously evolved and has surpassed the density of magnetic hard drives. By providing the largest storage capacity in the smallest footprint, 3D V-NAND has been leading the data center revolution in recent years. However, 3D-technology scaling faces several technical challenges [2]. (1) As the number of WL stacks increases the channel-hole etch process becomes a limit, since the total WL-mold height increases. (2) Interference between cells increases since the distance between WLs becomes smaller. (3) Faster data transfer speeds are required to support higher IO bandwidth.

A 1.2 V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package incorporating 16-die stacked 512-Gb NAND flash memories and F-Chip is presented. To meet the performance requirements of storage devices for higher capacity and faster data throughput, the 2nd generation F-Chip is developed. The F-Chip presents a dual bi-directional transceiver architecture including data retiming and training techniques to adaptively improve signal integrity. Besides, the F-Chip supports 1.2 V I/O for low power storage applications. This work, as a result, shows 33% improvement of eye-opening performances and 41% reduction of I/O power consumption compared to the previous generation.

The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.

NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and high-throughput performance. In recent years, a SATA interface supporting only up to 600MB/S throughput has hindered the accelerating performance growth of SSDs due to the host bandwidth limit. A PCI Express (PCIe) has emerged to close the limit because it can deliver 1GB/s throughput per lane and can be scaled to multi-lane to improve bandwidth [1]. Accordingly, the SSD performance bottleneck has moved from the host interface to the NAND flash interface. In a memory system, a die-stacking technology in a NAND flash multi-chip package (MCP) effectively increases capacity and throughput performance in terms of PCB complexities and power consumption compared to a method increasing the number of channels. However, the multi-drop bus topology on NAND interfaces severely affects I/O speed degradations due to channel reflections and inter-symbol interference (ISI) resulting from large capacitive loadings [2]. The undeniable paradox between larger storage capacity and higher I/O bandwidth has become a key challenge to reach enterprise-class SSDs. To overcome this issue, this paper presents a frequency-boosting interface chip (F-Chip) to boost I/O speeds while meeting capacity requirements. A 2Tb NAND flash MCP with 1GB/s toggle DDR interface is accomplished by incorporating the F-Chip into the NAND MCP including a 16-die stacked 128Gb NAND flash [3].

In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.

Generally, the main components of an autonomous driving system consist of perception (geometry recognition, localization, and objects detection & tracking) and navigation processes (global & local path planning, and controller). In this paper, the authors focus on finding an accurate position for an Unmanned Ground Vehicle (UGV) in urban environments. A GPS sensor is fundamentally used to get a current global position, but its accuracy is susceptible to satellite geometry or receiver's conditions; even though high performance guaranteed GPS such as differential GPS (DGPS) always return a precise position (position error is less than 0.4m) because of problems such as disconnection between base station and vehicle. The position errors, even a few meters, could engender serious accidents when an UGV is driving under urban environments. In this paper, the authors suggest the localization algorithm and novel lane detection algorithm. The detected lane information is implemented to overcome the GPS sensor's position errors. First, a novel lane detection algorithm is described, and then the localization algorithm is discussed. This paper also provides experimental results of the lane detection and the localization in an urban environment by using an UGV.

Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2–3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.

A computationally efficient and programmable dc-notch FIR filter design using a modified alpha - scaled sampling kernel and an analytic procedure is proposed. Design examples demonstrate that the proposed approach provides an efficient solution for designing a sharp dc-notch FIR filter, and satisfies the required filter specification.

We report on the development and demonstration of the watt-level operation of a compact green vertical external cavity surface emitting laser optically end-pumped by a single chip laser diode without any focusing lenses.

A 512Mb diode-switch PRAM is developed in a 90nm CMOS technology. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are described. Through these schemes, the PRAM achieves read throughput of 266MB/S and maximum write throughput of 4.64MB/S with a 1.8V supply.

We analyzed the effect of heat-spreader location on lasing properties of newly devised end-pumped vertical-external-cavity surface-emitting lasers in terms of the dissimilar behavior of pump beam redirection scheme and thermal lens effect.

In this report, we present the improved optical pumping efficiency in vertical external cavity surface emitting laser through the recycling the wasted pumping energy by employing the double band DBR which highly reflects a pump beam as well as a lasing one

We present the theory of intracavity optical second harmonic generation in VECSELs with well-known semiconductor laser rate equations. The theory is also included phase mismatching terms, which affects the nonlinearity available for the interaction.

A 256Mb PRAM featuring synchronous burst read operation is developed. Using a charge-pump system, write performance is characterized at 1.8V supply. Measured initial read access time and burst-read access time are 62ns and 10ns, respectively. The maximum write throughput is 3.3MB/S

A measurement method of resonantly enhanced gain profiles in vertical-external-cavity surface-emitting lasers is developed. By applying the method with LBO as intra-cavity frequency doubler, a second-harmonic-generation efficiency of 15% and a stable output power of 2 W are realized.

A nonvolatile 64-Mb 1T1R phase-transition random access memory (PRAM) has been developed by fully integrating chalcogenied storage material (GST: Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18-/spl mu/m CMOS technology. To optimize SET/RESET distribution, 512-kb sub-array core architecture was proposed, featuring meshed ground line and separated SET/RESET control schemes. Random read access time, random SET and RESET write access times were measured to be 60 ns, 120 ns, and 50 ns, respectively, at 3.0-V supply voltage with 30/spl deg/ C.