Search

Recent studies have shown that machine learning can improve the accuracy of detecting object boundaries in images. In the standard approach, a boundary detector is trained by minimizing its pixel-level disagreement with human boundary tracings. This naive metric is problematic because it is overly sensitive to boundary locations. This problem is solved by metrics provided with the Berkeley Segmentation Dataset, but these can be insensitive to topo-logical differences, such as gaps in boundaries. Furthermore, the Berkeley metrics have not been useful as cost functions for supervised learning. Using concepts from digital topology, we propose a new metric called the warping error that tolerates disagreements over boundary location, penalizes topological disagreements, and can be used directly as a cost function for learning boundary detection, in a method that we call Boundary Learning by Optimization with Topological Constraints (BLOTC). We trained boundary detectors on electron microscopic images of neurons, using both BLOTC and standard training. BLOTC produced substantially better performance on a 1.2 million pixel test set, as measured by both the warping error and the Rand index evaluated on segmentations generated from the boundary labelings. We also find our approach yields significantly better segmentation performance than either gPb-OWT-UCM or multiscale normalized cut, as well as Boosted Edge Learning trained directly on our data.

We report on the development of a hardware platform for integrated tuning and closed-loop operation of MEMS gyroscopes. The platform was developed and tested for the second generation JPL/Boeing post-resonator MEMS gyroscope. The control of this device is implemented through a digital design on a field programmable gate array (FPGA). A software interface allows the user to configure, calibrate, and tune the bias voltages on the microgyro. The interface easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip

Evolvable hardware is a recently proposed technology in which reconfigurable hardware under the control of an evolutionary (genetic) algorithm can automatically self-reconfigure into configurations with the desired behavior. This would not only enable the on-demand generation of new functionality when needed, but this could provide increased fault-tolerance, as the hardware would be able to cope with faults by reassigning function cells to take over the faulty ones. This paper describes ongoing work at JPL, focusing on applications to onboard image processing.