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Reaching the physical boundaries of the electronics-based communication approach has enabled photonic-based systems, which promise high-bandwidth and low power consumption, especially in multiprocessor systems, to be an alternative to electronic systems on chips. Real-time systems are specialized systems where tasks that cannot be completed in time cause high costs, and particularly communication with sensors and actuators have high importance. In this study, a sensor data distribution model is presented for multi-processor real-time systems that communicate with the photonic network on the chip. The study provides the distribution of the sensor data to the processors on the chip with the photonic infrastructure, and the results show that the proposed model is an effective approach for real-time systems.

The High Level Architecture (HLA) as a well-known IEEE standard for developing parallel and distributed simulation systems has been around for many years. In this paper, Runtime Infrastructure (RTI) of HLA is re-evaluated in the light of the current trends in many-core processor architectures. The future many-core processor architectures will contain thousands of cores connected with on chip networks. Such network on chip (NoC) architectures will not only be built as electronic networks but also as photonic networks. The communication links are established by using scalable communication patterns which define how the light paths to be setup in a 2D photonic network. In other words, RTI specific communication patterns orchestrate the underlying photonic network both to guarantee contention-free network operation and to utilize the bisection bandwidth available on the photonic torus. Time and data distribution management related algorithms are especially subject to this paper. Both the Greatest Available Logical Time (GALT) calculation algorithm and timestamp order (TSO) message delivery are carried out in small number of communication steps on 2D photonic torus. The approach taken in this work is based on hardware and software co-design.