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A metrological definition and a target value for linewidth roughness (LWR) in a gate pattern of MOSFETS are proposed. The effects of sampling interval gate-LWR measurements by critical-dimension scanning electron microscopy on measurement accuracy were examined by both experiment and simulation. It was found that a 10-nm interval is sufficiently small to fully characterize roughness in a typically chosen 2-nm-long line. Random image noise and intrinsic LWR variations are found to have larger effects on the measured LWR value than the finiteness of the sampling interval. A practical procedure for improving the measurement accuracy is also devised. Moreover, a meihodology for establishing the gate-LWR target is proposed. Threshold-voltage shift caused by gate-LWR is determined from the LWR spectrum and the 1-V curves of a transistor without LWR (i.e., ideal I-V curves). [ABSTRACT FROM AUTHOR]