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18. Impact of a Pocket Doping on the Device Performance of a Schottky Tunneling Field-Effect Transistor.

Author

Guin, Shilpi, Chattopadhyay, Avik, Karmakar, Anupam, and Mallik, Abhijit

Subjects
FIELD-effect transistors, METAL oxide semiconductor field-effect transistors, FIELD-effect devices, METAL oxide semiconductors, MATHEMATICAL optimization
Abstract

It is known that a pocket at the drain end of a Schottky barrier tunneling FET (SB-TFET) helps to improve the device performance in terms of greatly suppressed ambipolar current and reduced drain-induced barrier lowering (DIBL). A detailed investigation, with the help of a numerical device simulator, of the impact of using such a pocket either at the source end or at both the source and the drain ends of an SB-TFET is reported for the first time in this paper. The performance of the above-mentioned two devices is compared with a device having a pocket at the drain end and a conventional MOSFET. Optimization of the barrier height and the pocket parameters is made before performance comparison. It is observed that a pocket at the drain end helps suppress the ambipolar current and reduce both the subthreshold swing and the DIBL. On the other hand, a pocket at the source end helps to improve the ON-state current \(I_{\mathrm{{\scriptstyle ON}}}\) . Using a pocket at both the source and the drain ends results in overall improvement of the device performance. The effects of scaling on such device performance parameters are also reported. [ABSTRACT FROM AUTHOR]

Published
2014
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19. Impact of a Spacer–Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling.

Author

Mallik, Abhijit, Chattopadhyay, Avik, Guin, Shilpi, and Karmakar, Anupam

Subjects
FIELD-effect transistors, METAL oxide semiconductor field-effect transistors, ELECTRIC properties of silicon, ELECTRON tunneling, QUANTUM tunneling, ELECTRIC conductivity
Abstract

A tunnel field-effect transistor (FET) (TFET), in which the dominant carrier tunneling occurs in a direction that is in line with the gate electric field, shows great promise for sub-0.6-V operation. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer–drain overlap on the device characteristics of such silicon TFET is reported in this paper. It is demonstrated that a supersteep subthreshold swing and a significantly reduced off-state current IOFF can be achieved by appropriate designing of the spacer–drain overlap. An investigation of the influence of the drain potential on the device characteristics reveals that the absence of a tunnel-resistance limited region results in long-channel metal–oxide–semiconductor FET-like output characteristics for such a structure. Short-channel effects, such as drain-induced barrier lowering, are also greatly suppressed in it. Results of the investigation on the scaling properties of such devices are also reported. [ABSTRACT FROM AUTHOR]

Published
2013
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