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Deep Learning techniques have been successfully used to solve a wide range of computer vision problems. Due to their high computation complexity, specialized hardware accelerators are being proposed to achieve high performance and efficiency for deep learning-based algorithms. However, soft errors, i.e., bit flipping errors in the layer output, are often caused due to process variation and high energy particles in these hardware systems. These can significantly reduce model accuracy. To remedy this problem, we propose new algorithms that effectively reduce the impact of errors, thus keeping high accuracy. We firstly propose to incorporate an Error Correction Layer (ECL) into neural networks where convolution is performed multiple times in each layer and majority reporting is conducted for the outputs at bit level. We found that ECL can eliminate most errors while bypassing the bit-error when the bits at the same position are corrupted multiple times under the simulated condition. In order to solve this problem, we analyze the impact of errors depending on the position of bits, thus observing that errors in most significant bit (MSB) positions tend to severely corrupt the output of the network compared to the errors in the least significant bit (LSB) positions. According to this observation, we propose a new specialized activation function, called Piece-wise Rectified Linear Unit (PwReLU), which selectively suppresses errors depending on the bit positions, resulting in an increased model resistance against the errors. Compared to existing activation functions, the proposed PwReLU outperforms with large accuracy margins of up-to 20% even with very high bit error rates (BERs). Our extensive experiments show that the proposed ECL and PwReLU work in a complementary manner, achieving comparable accuracy to the error-free networks even at a severe BER of 0.1% on CIFAR10, CIFAR100, and ImageNet.

In this paper we demonstrate how performance of Edge-AI-Inference hardware can be enhanced by effectively using emerging commodity MRAM chips inside specific accelerator pipelines. We consider the special case of IoT-centric ‘normally-off/low-frequency’ AI inference workloads to benchmark the proposed approach. The proposed Non-Volatile AI Inference Accelerator (NVIA) is realized using FPGA and off-the-shelf MRAM chips. NVIA is benchmarked for Human activity recognition (HAR) dataset. Significant power gains, ∼9x (with Toggle-MRAM (180 nm)) and ∼750x (with STT-MRAM (22 nm)), were achieved compared to volatile SRAM.

In the aftermath of the 4th Industrial Revolution, AI and Big data technology have been used in various fields in South Korea, and the techniques are being applied to and complemented in various service fields which were implemented without them before. Especially, in order to secure credit stability for borrowed companies from financial institutions and to preemptively respond to the risks about—by means of online news articles and SNS data—the attempts to forecast the possibility of insolvency and adopt them into actual business are actively conducted by major domestic banks. In this study, we describe several analytical methods, outputs, and problems that are encountered during the processes of developing the unstructured text-based prediction system to detect the possibility of corporate insolvency—which ordered by a national government bank and discuss related issues with a real case. As a result, we have implemented an automatic tagger program for labeling largely unlabeled articles, and newly devised a prediction algorithm of the possibility of corporate insolvency. We achieved the accuracy of 92% (AUC 0.96) in aspect of performance and the hit ratio of 50% among the number of predicted 26 candidates that have the possibility of insolvency. Thus, the result of our study is revealed to be complementary to the financial data analysis sufficiently in performance, but yet have several limitations such as data coverage, reliability, and the characteristics of Korean language.

A biosensor with an alternating current-driven control is realized for label-free detection of biomolecule. This sensor precisely measures the capacitive changes in the electrode-electrolyte interface after hybridization with complementary DNA targets. Conventional capacitive biosensors generally use the excitation method with double current-sources. However these sensors have limitations due to performance-based issues of the DC potential drift and offsets, as well as weakness against common-mode noises. In this paper, the proposed device includes differential electrode pairs that are located in a single current-source line with sensing circuits, which results in the elimination of the effect due to the current mismatch. The device also shows an improved signal-to-noise ratio. Additionally, the individual control of the switch controller in this device offers robust and reproducible measurement capabilities independent of the duty asymmetry and pre-charged initial offset voltage. The device is a hybrid sensor that has both working electrodes and readout circuitry in one-chip using a CMOS process. The prototype successfully demonstrated the specific detection of oligonucleotide sequences. The device consumes 2.34mW from a 3.3 V supply in a 0.35 µm CMOS process.

A self-contained cartridge and an integrated instrument for the automated molecular testing are described. The proposed cylindrical cartridge consists of multiple chambers containing all necessary reagents such as specimens, lysis, wash, and elution buffers. The system provides a chain of automatic processes for the molecular test of sample preparation, amplification, and detection. Sample preparation can be fully conducted inside the cartridge, which includes reagents mixing, nucleic acids capturing, wastes-out, and eluates collection. The system also implements the amplifying and detecting processes of the extracted DNA using the peltier heating and photometry scanner, respectively. All flow movements in the instrument are driven by pneumatic actuations of syringe/piston sets and valve controls based on the motor driving. The molecular tests in the system were evaluated clinically using Salmonella bacteria. The performance of the system was verified successfully by comparing with the results from commercial equipment. The system including the disposable cartridge has the potentials to be applicable for point-of-care testing of molecular diagnostics such as Polymerase Chain Reaction (PCR) or other amplification methods such as isothermal amplification, resulting in an early diagnosis of disease.

Silicon devices based on impedance measurements offer label-free and direct electrical detection when used to quantify the hybridization of DNA molecules. They show rapid, robust, and inexpensive measurement and compatibility with commercial microfabrication technology. The real-time measurement of the impedance does not require the use of labeling molecules attached to the target DNA in optical and magnetic technology [1,2]. It also has the advantage of miniaturization for point-of-care (PoC) or on-site sensing applications, unlike the 3-electrode topology in electrochemical sensors [3]. Several studies have proposed capacitive biosensors that utilize a nonfaradaic process, which refers to transient currents charging a geometrical capacitor in an electrolyte-electrode interface [4]. Conventional capacitive biosensors using the excitation of the bidirectional current [5,6] can be implemented with a compact design, but they have several issues that degrade the sensitivity of the sensor, such as DC drift in the electrode caused by a charge imbalance, the electrolysis generated by DC voltage across the electrodes, the offset generated by pre-charged initial values, and weakness against common-mode noise. As a solution, we report a fully integrated capacitance-based biosensor that locates two electrodes differentially in a single current source.

This paper provides a complex band-pass filter (BPF) for low-IF conversion digital audio broadcasting (DAB) and terrestrial-digital multimedia broadcasting (T-DMB) tuner with I/Q gain and phase mismatch calibration. This calibration can be implemented in the first stage of complex BPF using feed-through resistor calibration scheme. The automatic tuning circuit with programmable clock is also presented. The measurement results show 1.536 MHz bandwidth with 2.048 MHz IF center frequency and 50 dB stop band attenuation at 0.7 MHz frequency offset. The in-band and out-band 3rd order intermodulation distortion (IMD3) are 55 and 60 dBc, respectively. After I/Q mismatch calibrating, 20 dB image rejection ratio (IRR) improvement is obtained from 38 dB to 58 dB in this work. The automatic tuning circuit guarantees less than +/- 4 % cut-off frequency variation covering the several clock requirements from demodulator ICs. The complex BPF is fabricated in 0.13 mum RF CMOS technology and consumes 9 mA with 1.2 V power supply.

A charge pump drive circuit for LED lighting is proposed. This circuit is realized with repeated use of a compact unit module consisted of a capacitor and diodes. The series-charge and parallel-discharge operation gives the efficiency better than the conventional converters with AC line input. This paper also shows how to minimize the number of modules for a given number of LEDs. A prototype implemented the charge pump drive circuit shows a maximum efficiency of 95% for 22 LEDs in series with the AC line voltage of 220 Vrms.

A fully on-chip CMOS VGA-based load- independent linear amplitude modulator is implemented for class E1, E2 power amplifiers of GSM/EDGE polar transmitter. By utilizing VGA-based 3-path architecture based on capacitor-free low-dropout linear regulator (LDO), the proposed circuit provides fast and stable operation at all-load conditions including open load when the battery varies from 3.4 V to 5.5 V. The small-signal bandwidth is wider than 5 MHz and the phase margin is bigger than 64deg at the worst-case-simulation condition. The circuit can stably drive output load-current of 0 to 1.6 A at a static bias-current of under 1 mA. The output voltage varies from 0.43 V to 3.2 V when the input reference-voltage VRAMP varies from 0.2 V to 1.5 V. The chip is fabricated in a TSMC 0.35 mum mixed-mode CMOS 2P 4M process and the size of pass transistor is 1.6 mm times 1 mm.

A fast switching charge dump assisted class-D audio amplifier is presented in this paper. To achieve high efficiency and high linearity, the Class-K* audio amplifier consists of the class D amplifier with high efficiency and the proposed charge dump amplifier with high linearity. The charge pump amplifier works at faster switching frequency than class D amplifier so as to compensate the distortion caused by switching of the class-D amplifier. The class-K* audio amplifier implemented in 0.35mum CMOS process shows -71.8 dB THD+N at 1 KHz and a maximum efficiency of 81% at an output power of 257 mW for 4.1Omega load.

A hybrid switching amplifier for dynamic power supply applications is presented. To achieve both high speed and high efficiency, a wideband buffered linear amplifier is combined with a hysteretic controlled switching amplifier. To obtain high linearity and reduce switching loss at low power levels where the switching amplifier is not needed, the linear amplifier supplies all load current with the switching one disabled. The novel two-quadrant linear amplifier as a voltage source for regulating the output voltage has very low output impedance of about 200 m Omega around the switching frequency, a high current-driving capability of maximum 220 mA and a bandwidth wider than 7 MHz. The hybrid amplifier can drive a circuit with an equivalent impedance of 7 Omega and supply a maximum output power of 1.1 W with a maximum efficiency of about 91%. Its output voltage ranges from 0.3 V to 2.9 V for a 3.3V supply. The chip is fabricated using only thick-oxide devices in a 0.13 um CMOS process and occupies an area of 3.9 mm2.

The current or voltage driving schemes are employed for pulse-amplitude modulation (PAM) in AMOLED displays. Current driving methods have advantages over voltage driving schemes including improvement of luminance uniformity at display panels and compensation of TFT characteristics at pixels. degrade the driving accuracy. This paper introduces a direct-type fast feedback current (DFFC) driver that offers fast settling time with good accuracy by comparing the data with the pixel current directly. An optimum compensation method for the feedback loop is suggested as well.

A UHF mobile single chip RFID reader is implemented in 0.18 mum CMOS process. Developed IC achieves DA output power of 3 dBm, OIP3 of 14.8 dBm, phase noise of -100 dBc/Hz at 100 kHz offset, noise figure of 35.5 dB for talk mode, 6.2 dB for listen before talk (LBT) mode, and current consumption of 108 mA from a 1.8 V supply. With an external PA, Tx output generates output power of 27 dBm with OIP3 of 42.5 dBm. A leakage signal cancellation scheme is employed to suppress inevitable Tx leakage into Rx input. At a distance of 90 cm between antenna and tag the average recognition ratio is increased from 0% to 42.8% by the leakage canceller.

We propose a new vehicle tracking system which can detect and monitor vehicles as they break traffic lane rules. Our proposed tracking scheme is based on characteristics of both traffic scene and vehicle. These include: background information, local position, and the size of a moving vehicle. The initial size and position of the vehicle are obtained using a 4-directional contour tracking method. The object contour is made less sensitive to luminosity changes by incorporating a frame differencing operation. Each vehicle can be described with four feature points. The template region is estimated by means of a minimum distance approach with respect to center position. Our experimental results confirm that extraction of feature points from each frame of the scene improves the efficiency of vehicle tracking systems. Furthermore, adjustment of the vehicle region with matched points of template resolves the previous problem of occlusion.

This paper presents a high linear and power-handling single-pole double-throw (SPDT) switch for WLAN 802.11 a/b/g applications. The switch circuit has asymmetric and stacked topology to have high power-handling and linearity for the Tx path. This SPDT switch has been implemented with 0.25 /spl mu/m GaAs pHEMT process by ETRI. The designed SPDT switch has the measured insertion loss of better than 1dB and isolation of better than 40dB for the Tx path and 25dB for the Rx path and the high power handling capability with P/sub 1dB/ of about 23dBm with control voltage of -3/0 V. The fabricated SPDT switch chip size is 1.8 mm /spl times/ 1.8 mm.

Air hoists are widely used in handling of heavy materials in industry. Conventional air hoists necessitate the operation of manual switches for vertical motion, thus the operator has a difficulty in operating of the switches and handling of material at the same time. To overcome such difficulty, this study develops a pneumatic control circuit for weightless material handling with air hoists. The pneumatic circuit memorizes the weight of load in terms of a pneumatic pressure. The pressure is then used as a feedback signal to achieve weightless handling of materials. To demonstrate the effectiveness of the proposed pneumatic circuit, handling forces and the response of the system for various material weights are examined through a series of experiments. The results show that the proposed pneumatic circuit for air hoists can be used in material handling with small manual operation force.

We have developed a 16 channel full add/drop WDM system for long-haul transmission and successfully demonstrated 16 channel 2.5 Gbps transmission over 640 km with single mode fibers and the repeater spacing of 80 km includes optical add/drop multiplexing (OADM). The space between the channels is 100 GHz. We tested the system in a 50/spl deg/C, 80% humidity and in a 0/spl deg/C, 0% environment to measure the wavelength change of the transponder output.