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This paper presents a memory binding algorithm for behaviors, used in application-specific integrated circuits (ASICs), that are characterized by the presence of conditionals and deeply nested loops that access memory extensively through arrays. Unlike previous works, this algorithm examines the effects of branch probabilities and allocation constraints. First, we demonstrate, through examples, the importance of incorporating branch probabilities and allocation constraint information when searching for a performance-efficient memory binding. We also show the interdependence of these two factors and how varying one without considering the other may greatly affect the performance of the behavior. Second, we introduce a memory binding algorithm that has the ability to examine numerous bindings by employing an efficient performance estimation procedure. The estimation procedure exploits locality of execution, which is an inherent characteristic of target behaviors. This enables the performance estimation technique to look at the global impact of the different[y;2036;13;1231;1;S] bindings, given the allocation constraints. We tested our algorithm using a number of benchmarks from the parallel computing domain. A series of experiments demonstrates the algorithm's ability to produce bindings that optimize performance, meet memory allocation constraints, and adapt to different resource constraints and branch probabilities. One limitation of our algorithm is that, in its current form, it is not well suited for system-on-a-chip synthesis where there is complex communication between general-purpose microprocessors that use custom-designed arrays. Results show that the algorithm requires 41% fewer memories with a performance loss of only 0.2% when compared to a parallel memory architecture. When compared to the best of a series of random memory bindings, the algorithm improves schedule performance by 22 %. [ABSTRACT FROM AUTHOR]

This paper proposes a novel circuit design methodology, called common-case computation (CCC)-based design, and new design automation algorithms for optimizing energy consumption and performance. The proposed techniques are applicable in conjunction with any high-level design methodology, where a structural register-transfer level (RTL) description and its corresponding scheduled behavioral (cycle-accurate functional) description are available. It is a well-known fact that in behavioral descriptions of hardware circuits (and also in software programs), a small set of computations often account for most of the computational complexity. However, in the hardware implementations (structural RTL or lower level), the common cases and the remaining computations are typically treated alike. This paper shows that identifying and exploiting common cases during the design process can lead to implementations that are much more efficient in terms of energy consumption and performance. We propose a new high-level design methodology with the following steps: 1) extraction of common-case detection and execution behaviors from the scheduled description; 2) simplification of the common-case behaviors in a stand-alone manner; 3) synthesis of common-case detection circuits and common-case execution circuits from the common-case behaviors; and 4) composing the original design with the common-case circuits to result in an optimized design. We demonstrate that the optimized designs reduce energy consumption by up to 59.8%, and simultaneously improve performance by up to 76.6%, compared with designs derived without special regard for common cases. The simultaneous improvements in energy and performance result in energy-delay product improvements of up to 90.6%. [ABSTRACT FROM AUTHOR]

Presents the high level power analysis and reduction algorithm. Use of device-level models for leakage; Estimation of the power consumption of the circuits due to leakage; Basis of leakage optimization.

Presents a study which presented a clock selection algorithm for control-flow intensive behaviors that are characterized by the presence of conditionals and deeply nested loops. Motivation; Clock selection algorithm; Experimental results and conclusion.

Deals with a study which presented a comprehensive high-level synthesis system that is geared toward reducing power consumption in control-flow intensive as well as data-dominated circuits. Review of the preliminary concepts; Presentation of the power estimation algorithm, based on switching activity matrices; Description of the synthesis algorithm; Experimental results of the study.

Presents a novel scheduling algorithm targeted toward minimizing the average execution time of control-flow intensive behavioral descriptions. Use of control/data flow graph model in algorithm; Application of algorithm to common benchmarks; Conclusions.