83 results on '"Kamakoti, V."'
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2. A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips
3. SHAKTI Processors: An Open-Source Hardware Initiative
4. ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance
5. SHAKTI-F: A Fault Tolerant Microprocessor Architecture
6. SER mitigation technique through selective flip-flop replacement
7. Framework for Selective Flip-Flop Replacement for Soft Error Mitigation
8. Approximate Error Detection With Stochastic Checkers.
9. ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs
10. Tunable stochastic computing using layered synthesis and temperature adaptive voltage scaling
11. PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information
12. Towards Quick Solutions for Generalized Placement Problem
13. A Simulation Based Buffer Sizing Algorithm for Network on Chips
14. Post-Synthesis Circuit Techniques for Runtime Leakage Reduction
15. Studies on the Performance of Two New Bus Arbitration Schemes for MultiCore Processors
16. Efficient Grouping of Fail Chips for Volume Yield Diagnostics
17. A genetic approach to gateless custom VLSI design flow
18. Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
19. Power Virus Generation Using Behavioral Models of Circuits
20. On Power-profiling and Pattern Generation for Power-safe Scan Tests
21. Controllability-driven Power Virus Generation for Digital Circuits
22. A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test
23. Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms
24. Efficient Building Blocks for Reversible Sequential Circuit Design
25. An area and configuration-bit optimized CLB architecture and timing-driven packing for FPGAs
26. Ultra folded high-speed architectures for Reed Solomon decoders
27. Tunable stochastic computing using layered synthesis and temperature adaptive voltage scaling.
28. SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis
29. Impact of Temperature on Test Quality.
30. Efficient Grouping of Fail Chips for Volume Yield Diagnostics.
31. Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.
32. PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test.
33. An artificial neural network guided parallel genetic approach to the routing problem for field programmable gate arrays
34. A principal component neural network-based face recognition system and ASIC implementation.
35. Detecting SEU-caused routing errors in SRAM-based FPGAs.
36. Placement and routing for 3D-FPGAs using reinforcement learning and support vector machines.
37. A universal random test generator for functional verification of microprocessors and system-on-chip.
38. A Framework for Automatic Assembly Program Generator (A^2PG) for Verification and Testing of Processor Cores.
39. A parallel architectural implementation of the New Three-Step Search algorithm for block motion estimation.
40. A bus encoding technique for power and cross-talk minimization.
41. A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.
42. A novel method for online in-place detection and location of multiple interconnect faults in SRAM based FPGAs.
43. A novel three phase parallel genetic approach to routing for field programmable gate arrays.
44. An efficient algorithm for the nearest smallers problem on distributed shared memory systems with applications.
45. An optimal parallel algorithm for the all-nearest-foreign-neighbors problem in arbitrary dimensions.
46. Efficient algorithms for prefix and general prefix computations on distributed shared memory systems with applications.
47. Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation.
48. Automatic Constraint Based Test Generation for Behavioral HDL Models.
49. Variation-Tolerant, Power-Safe Pattern Generation.
50. A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs
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