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How to promote the green and low-carbon transformation and ensure the supply reliability of the energy system has become an urgent problem to be solved on the development road of regional integrated energy system (RIES). In recent years, demand response plays an important role in reducing peak load, improving system reliability and power market flexibility. However, most of the existing demand response researches still study from the perspective of electricity system, do not fully consider the impact of other energy sources such as heat and cold on the system operation, and fail to take into account the economic benefits of both users and system. Therefore, the operation optimization model of RIES considering the demand response of cooling, heating and electricity flexible loads is established. In the model, the flexible loads are divided into translatable load, dispatched load and reducible load based on the energy consumption characteristics and the demand response potential. Simultaneously, the minimum comprehensive evaluation index is taken as the objective function to optimize the operation strategy and the load demand response plan of RIES. The results of case analysis show that the total cost of RIES and the peak to valley ratio of electricity is reduced by 3.70%, 27.6%, separately, which verifies the feasibility and practicability of the model.

Accurate delineation of the clinical target volume (CTV) and organs at risk (OARs) in pelvic plays a crucial role in the follow-up radiotherapy of the patient after hysterectomy. However, manual delineation is a time-consuming task which is susceptible to inter-observer variation. Automatic organ delineation is reliant on the global context contained in the extracted feature map to segment the original CT image. Currently, numerous deep learning networks, like U-Net++, are widely used in this task. In this paper, we use a standard U-Net++ as a fundamental structure followed by using dilated convolutions to replace its standard convolutions. We observed that dilated convolutions enlarged the size of the receptive field significantly, fusing more global contextual information and increasing the accuracy of segmenting organs. We evaluate the performance of standard U-Net++ and improved U-Net++(with double-deck dilated convolution) on the multiple organs segmentation in pelvic respectively. Our data set consist of CT images of 70 patients after hysterectomy. We use the dice similarity coefficient to quantify the segmentation accuracy. The result of our experiment demonstrates that the improved U-Net++ outperforms the standard U-Net++ on the segmentation of bladder, CTV and rectum. The dice scores show in follow: 93.2%±4.2% vs 91.2%±3.7% for bladder, 89%±3.6% vs 85%±2.6% for CTV and 87.6%±3.6% vs 84.7%±2.1% for rectum. It shows that the segmentation result of the improved U-Net ++ network is closer to the results manually drawn by the doctor than the standard U-Net++.

In the field of biomedical image analysis, segmentation is critical for disease diagnosis and treatment planning. While manual segmentation is tedious, time consuming and subjective due to the large shape and appearance variance among different subject, accurate and reliable segmentation is very challenging for automatic segmentation methods at the same time. In this paper, we present our recent effort on developing a reliable segmentation algorithm in the form of a convolutional neural network. Our network architecture is inspired by the popular U-Net and its variation (3D U-Net) and has been carefully modified to maximize bladder and rectum segmentation performance. We transfer our data to four channels to augment the data and prevent overfitting. The Dice similarity coefficient (DSC) is used to evaluate the network's performance. The outcome of experiments demonstrates the superiority of the proposed method.

Increasing power density in the microelectronic devices has led to thermal management concerns to ensure efficient, reliable, and long-term operation. As device dimensions continue to decrease, the interfaces of dissimilar materials (e.g., metal-semiconductor) may limit heat removal from the device active region. Improving the thermal transport across interfaces is a necessary consideration during the design process and necessitates accurate measurement of the thermal boundary conductance (TBC) and understanding of transport mechanisms. In addition, low-dimensional materials, such as 1D nanotubes and nanowires and 2D sheets, have attracted considerable interest because of their unique physical properties and small footprint. Two-dimensional transition metal dichalcogenides (TMDs) have been studied extensively for their electrical properties, including the metal-TMD electrical contact resistance, but the thermal properties have received much less attention. We measured and analyzed the TBC across Al-Ti-MoSe 2 -SiO 2 interface using time-domain thermoreflectance. The results are an order of magnitude larger than previously reported values at MoSe 2 -Au interfaces, but still near the low end for typical metal-semiconductor interfaces.

This paper proposes a compact delay matching solution for reference clock in PCB. The proposed method provides up to 70% area saving compared to the traditional length matching methods. It also provides design and layout flexibility. Effectiveness of the matching network, electrical static performance, and component variation impacts are simulated and compared to conventional methods.

Jitter is a critical factor to the performance of highspeed signal links. Jitter can be modeled as a random process. Both the probability density function (PDF) and the spectral characteristics of the jitter are important for evaluating the impact to the channel performance. The concept of numerical conditional probability density function (NCPDF) and a new statistical method called FastBER are proposed in this paper to accurately and efficiently perform the bit-error-rate (BER) analysis with taking into account both the PDF and the spectral characteristics of an arbitrary jitter sequence for arbitrarily low BER levels.

In this paper, novel through hole/embedded absorbers based on absorbing materials are used to suppress the cavity resonant effects of power delivery networks (PDNs) in printed circuit boards (PCBs). The proposed technique can substantially reduce PDN impedances and EMI, and improves the signal and power integrity of interconnects for computer and electronic system designs. The embedded absorbers can be implemented by drilling through holes or/and arbitrarily shaped slots in the PCB or package, and then filling in the holes/slots with absorbing materials. As an example, full wave simulations are performed and results show that the proposed technique significantly reduces PDN impedances and radiated electric fields from PCB, though it is generic technique for mitigating other issues including crosstalk which are caused by PDN cavity resonant effects.

Determining how to accurately estimate and control the loss of a channel is critical to the success of the design of a high-speed I/O link. As Printed circuit boards (PCB) continue to be a key ingredient of a computer system design, the cost-effective characterization of the PCB materials and the measurement of the loss PCB traces in a given stackup have become a necessary step in the computer design cycle. In this paper, the measurement methods for the PCB trace loss are discussed and compared. A cost-effective method, namely Delta-L, is introduced and analyzed in detail. The method has been widely applied in the loss characterization of PCB traces in the server computer system designs. The simulation and measurement results are presented to show the effectiveness and accuracy of the method.

In this paper through integrating absorbing materials onto a probe as terminators to eliminate the reflected noises on device under test (DUT), a novel on-probe termination technique is introduced for high frequency measurements. Absorbing material is suitable for on-probe termination, since there is no need of “ground” which is required in conventional resistive termination, and it also provides better flexibility in on-probe design. Measurement are performed to test the feasibility of proposed technique. Results show absorbing terminators can effectively terminate reflected signals and eliminate noises. The proposed technique provides innovative on-probe termination solution for cost reduction or/and feasibility improvement in high frequency measurements.

This paper presents a practical method to mitigate crosstalk in flex circuit due to high density routing. The method will maintain the routing density while the signal integrity performance will be improved. Practical flex construction method is also proposed for high speed flex interconnects between two chips. The effectiveness of the method is proved by 2D/3D modeling of the flex transmission lines.

A novel method called SNEM (full S-parameter synthesis from near-end measurement) is proposed to obtain the full S-parameter matrix by probing only a subset of all the ports of a passive linear network. Other ports that are not probed need to be terminated by various impedance values. A termination error correction algorithm and a guideline for choosing termination impedance values have also been developed to make the method robust, accurate, and efficient. Examples are included in this paper to demonstrate the applications of the SNEM method in integrated circuit (IC) package, on-die structure, and socket/connector characterizations. The method has been validated by both simulations and lab correlation.

In this paper, a technique is proposed to improve the electrical performance of high speed signaling through direct printing additional dielectric or other types of materials onto the PCB interconnect using inkjet printing. Inkjet printing is used to coat thin film or other structures onto the microstrip, via pad, pin field, or other structures on PCB. The electrical performance of interconnects can be adjusted and improved through such process. As an example, Inkjet printing can be used to increase the dielectric thickness of microstrip cover layer (soldermask), and thus to suppress the far end crosstalk and improve the insertion loss. This potentially is better than conventional PCB manufacturing techniques such as photo-lithography, which requires many process steps, which lead to higher cost and longer development time.

In this paper, through introducing the short and open standards and excluding the match (termination) standard, a technique is proposed to simplify the measurement of symmetric device under test (DUT). Because the short and open standards are usually easier to obtain than the match (termination) standard in terms of cost and/or feasibility, this technique provides more cost-effective and more flexible solution for characterization of symmetric systems and interconnects.

As integrated circuit (IC) chips keep growing in size, I/O data rates and complexity, electrical margin left on printed circuit board (PCB) gets smaller. Mid-loss or even low-loss material may be needed in more cases to meet high speed (HS) signal routing length requests, which leads to cost-adder on PCB. This submission introduces analysis flow as well as practical methods targeting reducing PCB material cost through SI architecture optimization. Following the analysis flow, board designers can get better opportunity of using cheaper material without sacrificing performance.

Microorganism detection through computer vision is of great essence in many scientific and industrial fields, among which vorticella is always a challenging and focused topic, especially for the sake of water quality monitoring and biological diversity tracking. However, given the fact that vorticella is likely to be obscured by alga and it float in different poses, the visual detecting method must be tolerant of different rotations and slight ambiguity. Previously, the Histograms of Oriented Gradients (HOG) is widely used in pedestrian, hand gesture and many other object detections. And the Local Binary Pattern (LBP) has been proven to be a widely applicable image feature for texture classification and face analysis. By combining the two methods, this paper presents a method to build rotation-invariant descriptors, in which the idea of dividing whole image into spatial blocks to obtain local relative distribution and the concept of utilizing the discrete Fourier transform (DFT) on cycle-shift patterns in histogram to acquire rotation-invariant features are efficiently bonded.

Channel loss is a dominant factor for the signaling performance of high-speed I/O's. Some platform design guides clearly specify the printed-circuit board (PCB) trace-only loss requirement. The via effect has a big impact on the loss of the entire channel and how to characterize the loss of a stripline design with the via effect being de-embedded is very important for a designer to select the right material and manufacturing process control, balancing the platform cost and performance requirement. An improper selection of PCB material may result in either a costly over design or an increased risk of platform performance. This is especially true for traces on a thicker board with long via or any board with long via stub. Furthermore, the impact of via and via stub is more prominent when low-loss PCB material is used. A few methods for PCB trace loss characterization have been widely used in the industry, including Thru-Reflect-Line (TRL), Delta-L and Smart Fixture De-embedding (SFD), to remove the unwanted via effect in striplines. Some of methods, such as TRL, require a series of measurement procedures with many de-embedding structures. How to effectively remove via effect through a simple, efficient, and accurate approach in the high volume measurement is critical for platform designers, as well as PCB suppliers. In this paper, a study on PCB insertion loss measurement metrology is conducted to compare the accuracy and efficiency of different characterization methods.

This paper reports a microfluidic enabled print-to-screen (P2S) platform, which can achieve low-cost, high-throughput, high-precision printing with plug-and-play disposable cartridge, as well as parallel screening with minimized crosstalk. The performance of the P2S platform is characterized and, using this platform, the cell-killing performance of 3-out-of-10 drug combinations towards ovarian cancer cell is, for the first time, studied and as a result, 15 out of 175 drug combinations are newly identified to exert potent cancer cell toxicity. This demonstrates the potent applicability of P2S platform for combinatorial chemotherapy, which can greatly speed up the entire cycle of drug cocktail discovery.

In PC/Server industry, simulation process is usually separated into pre-layout and post-layout phase. The pre-layout simulation focus in finding the solution space or choosing a better topology [1], [2]. For post-layout simulation, extracting 3 or 5 pairs of the channel model and conducting the simulation analysis is widely used. However, it requires a basic understanding of the layout. Otherwise the channel which is extracted may not be the best one to represent the worst scenario in the reality. The system level interconnect electrical performance characterization, which can consider a whole interface or even multiple interfaces, become an efficient way, especially estimating the risk of an out-of-guideline design. In this paper, a process with less human interaction is demonstrated. This method can relief the burden in choosing the representative channel from the layout and allow the designer to focus in improving the layout quality in these problematic areas.

Channel noise scan (CNS) approach is proposed in this paper to efficiently analyse the potential VR-signal coupling issue in the post-layout printed circuit board (PCB) check and the post-silicon debugging of the platform development. CNS is based on a new simulation methodology that includes the whole PCB with signals, voltage regulator (VR) networks, and the interaction. A frequency domain indicator is proposed to systematically analyse the VR-signal coupling problems. This methodology can also provide the ability for the designer to do performance/cost trade-off, layout optimization.

Dual-stripline is widely used in the computer systems to save printed circuit board (PCB) cost and achieve more compact form factor. Many design parameters can affect the overall performance of the dual-striplines. In this paper, the optimization of the dual-stripline design is discussed in detail, such as stackup selection, component breakout, etc. Theory analysis as well as Three-Dimensional full-wave modelling results of the inter-layer crosstalk for both single-ended and differential dual-stripline are presented to understand the inter-layer crosstalk. Measurement data from a test board is used to correlate the modeling result. An end-to-end simulation flow is proposed to precisely evaluate the overall crosstalk and full-link performance of a design with dual-stripline.

Cavity Resonant Edge Effects (CREE) in printed circuit boards (PCBs) and packages can cause severe power integrity (PI) and electromagnetic interference/compatibility (EMI/EMC) issues. Electromagnetic radiation from PCB edges are major sources of EMI/EMC problems in electronic devices. Power supply noise, in the form of fast changing currents (di/dt), traverses the power-return paths of PCBs and packages using power vias. CREE produces considerable level of noise along the edges of PCB and package power planes due to signal coupling between vias and reflection along PCB edges with transient currents. In this paper, we investigate an approach to minimize cavity resonant noise by placing absorbing material along the edges of a PCB board. The upper peak (anti-resonant) impedance of the power distribution network (PDN) is reduced significantly. In this paper the simulated example shows the absorbing material reduces the upper impedance peaks as much as to 8% comparing to the impedance peaks without absorption material. Conclusively, the results show that adding absorbing material along the PCB edges significantly improves the noise issues by suppressing CREE.

The paper presents a rigorous, one-port measurement technique for the characterization of on-chip pad response, particularly the pad capacitance (Cpad). By adding two independent (“short” and “match”, or two terminations with known impedance other than “open”) standards to the existing one-port method, the method eliminates the errors in the current vector network analyzer (VNA) method, while providing frequency-dependent data. This not only overcomes the fundamental restriction in conventional two-port measurement methods that are prohibitively complex, but also is better than existing one-port methods that are inaccurate due to lack of two independent measurements. Simulations and experiments are performed to validate the proposed method in the paper.

In this paper, channel noise scan approach (CNS) is proposed to efficiently analyze the potential VR-signal coupling issue in the pre-silicon design and the post-silicon debug of the platform development. CNS is based on a new simulation methodology that includes the whole PCB with signals, voltage regulator (VR) networks, and the interaction between the two. The goal of this simulation methodology is to help platform developer to quantify the VR-signal coupling risk and find the outliers of the victim signal nets according to the board layout and the VR design. This methodology can also provide the ability for the designer to do performance/cost tradeoff, layout optimization. To systematically analyze the VR-signal coupling problems, both the frequency and time domain approaches have been developed to characterize the VR-signal coupling in different levels. The frequency domain approach can quickly point out potential issues and the time domain approach is proved to be consistent with the frequency domain but with more detail and intuitive information. A design flow is given to efficiently identify the outliers of victim signals by VR noise coupling impact. Designers can improve the layout based on channel noise scan results from the simulations.

The via effect has a big impact to the loss of the entire channel. To characterize the loss of a stripline design without the via contribution is very important for a designer to evaluate the dielectric material selection and the manufacturing process control. In this paper, an effective methodology, namely Delta-L, was proposed to remove the via effect efficiently and characterize the board electrical performance accurately.

In this paper, the signal integrity (SI) simulation and computer system electrical design flow is discussed. Traditionally, the SI analyses lead to a set of physical design rules that the printed-circuit board (PCB) and integrated circuit (IC) package designers rigorously follow in the layout to ensure the signaling performance meets the requirements. Such practice makes the signaling requirements intuitive to the layout engineers. But, at the same time, it may also reduce the design flexibility and limit innovation. To bridge the gap between physical design and signaling performance, the concept, ingredients, and flow of an electrical design checker is introduced and described in detail. The flow has been applied to the various designs, and results are discussed.

In a server system, the switching voltage regulator (VR) noise coupled to the IO pins of the adjacent memory riser connector through the open air above the base board, and the link performance was impacted by the coupling. A simulation flow was developed to reproduce this EMI phenomenon. The flow first used electromagnetic field solvers to extract the VR related power network and the VR-IO coupling network, and then the di/dt and dv/dt noise sources and the induced IO noise were solved in HSpice®. The simulation revealed the underlying coupling mechanism: The high frequency current loop formed by the power MOSFET, the VR power shapes, the snubber RC circuit at the bottom layer of the board, and the stitching via acted as a transmitting loop antenna, and the radiating field propagated through the air and was picked up by another loop (receiving antenna) formed by the riser connector pins. An effective mitigation method is to use bigger snubber resistor to damp this near field radiation. Both the coupling theory and the effectiveness of the mitigation method were proved by the measurements.