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A 5V-input, high-frequency, high-density (9A/mm2) buck converter featuring a low-voltage GaN power transistor (with 5-10× better FoM than Si) with on-die gate clamps, integrated with a CMOS companion die in 4mm × 4mm package, achieves 94.2% peak efficiency for 5V in /1V out at 3MHz switching frequency with a 40nH inductor.

A dual-input, digital hybrid buck-LDO system featuring 300MHz Fully-Integrated Voltage Regulator (FIVR) and Computational Transient Management Controller (CTMC) based Low Dropout (LDO) regulator is presented. The high speed, parallel CTMC-LDO reduces the FIVR input resonance (82% pk-to-pk voltage-swing reduction). The CTMC-LDO operates without any communication with FIVR and can act as a clamp (54% droop & 69% settling time reduction) or share current (0-100%) in parallel with the FIVR, thus increasing load capacity.

A 1S direct-battery-attach buck converter with a 5-stack, thin-gate-FinFET power train delivers a peak efficiency of 89.2% for a 3.8V in to 1.8V out, with 10x higher power density (~15A/mm2), switching at up to 10x higher frequency (40MHz) using 4x-10x lower inductance (10-100nH) than state of the art. Cascaded self-timed drivers and soft-switching low-side drivers minimize complexity in driving 10 individual power switches safely.

High-performance many-core processors and GPUs demand 100s of Watts of power in a single voltage/power domain on chip, operating below 1V. High-frequency and highcurrent-density fully integrated voltage regulators (FIVRs) with in-package air core inductors (ACIs) [1] or on-package magnetic inductors can deliver power with high efficiency and low distribution losses in compact footprints. Multiple FIVR tiles must be “ganged” to support the large on-chip voltage/power domains while meeting the reliability constraints of the active and passive elements, and maintaining high overall efficiency.

Elegant integrated circuit design techniques are required to further enhance the performance of the next generation of DC-DC converters for various applications such as multi-core microprocessors, energy harvesting, automotive electronics and LED drivers. Novel hybrid combinations of inductors and capacitors, minimizing passive components sizes by operating at GHz, recycling energy from gate drivers using bond wire inductors, and using a single inductor for multiple output power paths for minimal cross-regulation, are some of the techniques presented in this session demonstrating the latest in DC-DC converters at both system and circuit levels.

A dual-rail hybrid analog/digital LDO achieves both high efficiency and tunable high PSRR simultaneously using a dynamic current steering mechanism. Measurements on a 22nm CMOS test chip demonstrate up to −46dB PSRR and 89% efficiency across 0–80mA load from1.8V/1.05V dual-input rails.

An AES engine with uniform side-channel-attack (SCA) resistance across time/frequency domains using a high-bandwidth non-linear digital low-dropout (NL-DLDO) regulator in conjunction with AES arithmetic countermeasures is fabricated in 14nm CMOS. Randomized regulator loop parameters and cascading LDO and arithmetic transformations provide >250K× increase in frequency/time-domain MTD, with no CPA attack detected on current/electromagnetic (EM) traces measured from 1 billion encryptions.

A 2-input/4-output autonomous RPDN in 14nm CMOS with dynamic current steering enables better core-count and FIVR scalability for many-core SoCs in scaled process nodes while improving the overall area efficiency of on-die power delivery/management circuits by 35%. The RPDN controller minimizes losses for a variety of operating conditions to improve overall energy efficiency in most runtime scenarios while complying with all local and global current limits.

This work presents a summary of the digital control techniques in todays advanced, state of the art IVRs and the role digital control is playing to enhance their key performance metrics. Examples from high switching frequency Buck converters, computationally controlled digital LDOs as well as digitally assisted analog and hybrid LDOs speaks not only to the growing popularity of digital control in a wide variety of applications but also demonstrates its suitability on advanced process nodes which is inherently tough on analog circuits.

Computationally-secure cryptographic algorithms when implemented on physical platforms leak critical physical signals correlated with the secret key in the form of power consumption and electromagnetic (EM) emanations. This can be exploited by an adversary, leading to side-channel attacks (SCA) that can recover the secret key. Circuit-level on-chip countermeasures include a switched-capacitor current equalizer [1], charge-recovery logic [2], an integrated voltage regulator (IVR) [3], and an all-digital low-dropout (LDO) regulator [4], which suffer from performance degradation, high power/area overheads because of large embedded passives, as well as EM leakage from large metal-insulator-metal (MIM) capacitor top plates. Alternatively, simulations of shunt LDO-based regulators have been shown to be effective for power SCA resistance [5]. Noting that the correlated current is the source of both power (at supply pin) and EM leakage (radiation throughout current path), this work embraces current-domain ‘signature attenuation’ (CDSA) as a low-overhead generic countermeasure against both EM and power side-channel attacks to achieve the highest minimum traces to disclosure (MTD $> 1\mathrm{B})$ reported to date.

A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven computational controller (CC) is presented, which computes the required number of power gates (PGs) unlike the traditional IIR filter-based control techniques to regulate the output voltage for any load/reference transient. The CC ensures ~ns transient response with a deterministic two-event duration settling time, independent of the dynamic range of the load or output capacitor value. Measurement results of a 10-bit PG design demonstrate a droop of 100 mV for 500 mA (2 A/ns $di/dt$ ) with settling times < 20 ns. The CDLDO design is presented with the key equations and timing diagrams to show the operating principle of the concept. Methods to accommodate resiliency to process, voltage and temperature (PVT) and wide dynamic voltage frequency scaling (DVFS) conditions are also discussed in detail.

Complex SoCs in scaled CMOS processes integrate a large variety of digital, SRAM and noise-sensitive mixed-signal/analog circuit blocks such as PLLs, wireline/wireless/RF transceivers, sensor front-ends, etc. The on-die low-dropout regulators (LDO) used for fine-grain DVFS of digital and memory blocks must respond fast to large load transients to minimize voltage droops/overshoots without using large decoupling caps, while minimizing power overheads over a wide operating range. The noise-sensitive analog circuits, on the other hand, need LDOs that provide sufficiently high power supply rejection (PSR) and minimal output voltage ripple, while maximizing current efficiency. Fast and scalable digital (DLDO) [1], analog-assisted digital (AA-DLDO) [2]–[3] and hybrid (HLDO) [4] analog-digital LDOs targeted for digital and memory blocks, as well as high-PSRR analog LDOs (ALDO) [5] optimized specifically for analog circuits have been recently reported.

Fully Integrated Voltage Regulators (FIVR) with package-embedded air-core inductors [1] or on-die solenoid inductors with planar magnetic core [2] promise efficient power delivery and fine-grain wide-range DVFS in complex SoCs while providing fast transient response. The FIVR must provide high conversion efficiency across a wide operating range of output voltages and load currents, including light to medium loads, to maximize the overall energy efficiency of the SoC across different power states. Phase shedding and switch scaling have been used for high-frequency FIVR designs with pulse-width modulation (PWM) control in continuous conduction mode (CCM) to maintain high efficiency for large load currents [1–5], and pulse-frequency modulation (PFM) and hysteretic control have been used to achieve high efficiency across light to medium loads [3–5]. In this paper, we present an FIVR in 14nm CMOS with a 2.5nH air-core inductor embedded in an ultrathin coreless package $( 200 \mu m$ thick) (Fig. 8.5.7), featuring self-trimmed, soft-switched and digitally controlled variable ON-time DCM operation up to 70MHz to achieve high conversion efficiencies across light to medium load currents ranging from 5mA to 500mA and wide 0.7-1.2V output voltage range. The FIVR uses a cascoded thin-gate powertrain (Fig. 8.5.1) to support input voltages up to 2Vmax with the cascode bias rail set at $V_{in} /2$ which consumes $\lt/p\gt\lt1$ uA at light load. A small thick-gate device is connected across the inductor to dampen oscillations when the power stage is in a high-impedance state. The output voltage is monitored by a comparator with sub-ns response time which triggers an inductor current pulse when the output drops below the reference voltage. A resistor divider with a feedforward capacitor is used to achieve fast response time.

A 25MHz switching, event driven, 6-input and 9-output single inductor Energy-Harvesting PMIC (EHPMIC) with multi-modal harvesting capability from DC & AC sources delivers up to 120mW with a peak efficiency of 81.7% and only 120µW control power overhead. The high-frequency, high-bandwidth design optimally trades off EHPMIC conversion efficiency with inductor/capacitor size & transient response speed to enable the fast power state transitions demanded by the SoC in a compact IoT edge node, thus minimizing the overall platform size & energy consumption.

A digitally controlled LDO in 14nm tri-gate CMOS powering an Atom™ core with embedded power gates enables per-core DVFS over a wide voltage-frequency range. The LDO demonstrates 99.6% peak current efficiency at 2.5A load current and provides a power density of 26.1 W/mm2. The multi-mode digital controller featuring non-linear mode and adaptive gain achieves

In this paper, we propose a digitally controlled voltage regulator with fast-transient-response using an oscillator based ADC implemented in 14nm CMOS technology. The transient response is critical to mitigate droop for large di/dt seen in cores and wide dropout range helps enable DVFS to improve power/performance ratio. In this work, we target 1-1.15V input voltage with output voltage range of 0.5–1.12 V with minimum 30mV dropout, and load current range of >22× with 0.1A–2.2A at 50mV dropout with

Fully integrated on-die buck voltage regulators (VR) promise efficient and wide-range local power delivery and management capability with fast transient response for fine-grain DVFS domains of high power density in complex SoCs. Integration of high-quality power inductors that can support high current density with minimal losses is a major challenge.

One of the major sources for the petroleum products is obtained from the seas (offshore and onshore). Here the major problem faced by the worker is maintaining the required pressure and flow till the extreme ends. In this paper, the parameters such as pressure and flow are maintained constantly by implementing control valves depends on the different pressure and flow rate of the transmitting pipe and these parameters are monitored and controlled using HMI screen. Hence the automation in pipeline transportation system is an important research area. In order to fulfill the above requirement, there is a continuing need for research on improved forms of control. Hence PLC (Programmable Logical Controller) is used to automatically regulate the flow and pressure of the petroleum product by controlling the percentage of opening of the control valves. The required set point for pressure and flow are obtained by implementing a suitable controller that regulates the pressure range and flow rate in the long transmitting concrete pipes. For this, a PLC based controller is developed and their closed loop response is identified and the simulation is carried out to ensure the performance of the controller.

Monolithic integration of Voltage Regulators (VR) is challenging given the inherent lack of scalability of inductor. Circuit techniques to reduce inductor size are attractive to increase power density and scalability. This paper presents a 70∼72% efficient, 500MHz digitally controlled 3-level Buck VR with a fully on-die spiral inductor implemented on 22nm Tri-Gate CMOS with MIM capacitors. The advantages of the 3-level converter for wide range Dynamic Voltage & Frequency Scaling (DVFS) over traditional solutions like linear regulators & Buck VRs are demonstrated.

An all-digital method of pseudo randomly varying switching frequency of a buck VR in non-linear low power modes (hysteretic and pulse frequency modulation) is proposed in order to reduce acoustic noise. The switching frequency is maintained within the audio range, instead of being increased, and hence switching losses do not increase. The random variation in switching frequency in this scheme converts tonal noise to white noise which has lower peak power and is less noticeable to humans.

Switched reluctance motor (SRM) has developed into a competitive choice for many applications of electric machine drive systems in recent times due to its relative simple construction and robustness. The advantages of SR motors are highly reliable, good performance and reduces the maintenance. The absence of windings in rotor and permanent magnets gives possibility to achieve very high speeds (above 10000 rpm) and turned SRM into perfect solution for operation in hard conditions like presence of vibrations or impact. Such simple mechanical structure greatly reduces its price. This paper presents detailed analysis, and modeling of six dfferent type of converters used in with three phase switched reluctance motor (SRM). These converters are Asymmetric, Bifilar, Auxiliary, High Demagnetization-dump, C-dump type. These converters are simulated by MATLAB/SIMULINK package. This paper introduces, why the asymmetric bridge converter is the best one for Switched reluctance motor in high speed with torque ripple reduction.

This paper mainly contributes to reduce the environmental effects induced by the combustion of coal that results in the emission of toxic sulphur dioxide (SO 2 ). For the reduction of SO 2 , Flue Gas Desulphurization (FGD) is the most commonly used method. In our work, mathematical modelling of hydrogen peroxide based FGD has been developed. A fuzzy based PID controller is developed for SO 2 emission control process using MATLAB/SIMULINK platform. By selecting appropriate fuzzy rules, the parameters K p , K i and K d of the PID controller are tuned and the performance of the developed fuzzy based PID controller is compared with the conventional controllers such as ZN (Ziglar-Nichols) and IMC (Internal Model Control) PID controllers. The error indices such as ISE, IAE, ITAE and quality indices such as t r , t s , %Mp of the developed fuzzy PID controller produce better control actions than conventional ZN and IMC PID controllers.

This article presents the design and construction of Model Predictive Controller (MPC) for a Pulse Width Modulation (PWM) based buck converter, working in Continuous Conduction Mode (CCM). The converter operates at a switching frequency of 100 KHz. The buck converter is mathematically modeled and implemented in matlab simulink The open loop response of the buck converter is used to obtain the transfer function (second order) of the model, which in turn is used to design the MPC controller. This MPC is used to control the output voltage of the buck converter and it has been found that the output voltage is maintained constant accurately for dynamic load, and the peak overshoot is reduced drastically. The output voltage obtained with MPC controller is then compared with the output voltage obtained from fuzzy based buck converter and it has been observed that the MPC gives better output than the fuzzy controller.

A fully on-die, digitally controlled, 500MHz switching, 250mA rated output buck Voltage Regulator (VR) implemented in 22nm Tri-Gate CMOS is presented. The silicon measured a peak efficiency of 68% and consumed an area of 0.6mm 2 (without output decoupling) with a power density of about 410 mW/mm 2 . The paper also demonstrates a controller bandwidth of 43MHz; the highest reported to date for any digital controller, resulting in output voltage ramp rates as high as 10V/μsec.

Systemic Lupus Erythematosus involvement of the kidneys is associated with high morbidity and mortality. Inter-observer variability can also lead to an incorrect assessment of the disease. Computer aided image analysis can potentially be used to advance the understanding, diagnosis and treatment of Lupus. Our research focuses on the image analysis of kidney biopsies for quantifying tissue characteristics relevant to Lupus. In this paper we describe an algorithm for identifying glomeruli in H&E stained mouse renal biopsies. The proposed approach uses color segmentation to identify all objects in the image that potentially correspond to the Bowman's space around the glomeruli. This is followed by a perceptual grouping procedure to group objects based on their size, location and orientation.

This paper introduces a new architecture for a fully synthesizable digital delay line (DDL) used in digitally controlled voltage regulators. The new architecture uses a variable number of delay elements to lock to the clock frequency depending on the actual process corner and the temperature variations. Also, a comparison between the proposed scheme and the conventional delay line with discretely programmable delay cells is presented. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32 nm technology. The comparison shows that the proposed architecture has better linearity, area, and a fast calibration time with respect to conventional delay lines.

A decade bandwidth 90 W, GaN HEMT push-pull power amplifier has been demonstrated. The power amplifier exhibits 18 dB small-signal gain with 20-1100 MHz 3-dB bandwidth and obtains 82.2-107.5 W CW output power with 51.9-73.8 % drain efficiency and 15.2-16.3 dB power gain over the 100-1000 MHz band. The push-pull power amplifier occupies a 2 x 2 inch PCB area and uses a novel compact broadband low loss coaxial coiled 1:1 balun to combine two 45 W packaged broadband lossy matched GaN HEMT amplifiers matched to 25 U. The packaged amplifiers contain a GaN on SiC HEMT operating at 50 V drain voltage with integrated passive matching circuitry on GaAs substrate. These amplifiers are targeted for use in multi-band multi-standard communication systems and for instrumentation applications.

The authors present a cyber-physical systems related study on the estimation and prediction of driver states in autonomous vehicles. The first part of this study extends on a previously developed general architecture for estimation and prediction of hybrid-state systems. The extended system utilizes the hybrid characteristics of decision-behavior coupling of many systems such as the driver and the vehicle; uses Kalman Filter estimates of observable parameters to track the instantaneous discrete state, and predicts the most likely outcome. Prediction of the likely driver state outcome depends on the higher level discrete model and the observed behavior of the continuous subsystem. Two approaches to estimate the discrete driver state from filtered continuous observations are presented: rule based estimation, and Hidden Markov Model (HMM) based estimation. Extensions to a prediction application is described through the use of Hierarchical Hidden Markov Models (HHMMs). The proposed method is suitable for scenarios that involve unknown decisions of other individuals, such as lane changes or intersection precedence/access. An HMM implementation for multiple tasks of a single vehicle at an intersection is presented along with preliminary results.

In general the idea of remote monitoring of various equipments and devices over the Internet is becoming a desirable practice in the process plants industries over the few decades. Over the years, there has been constant increase in the development of industrial automation through remote monitoring and diagnosis virtually through computers and Internet. The strong emphasize on the automatic XML report generation for the real-time process in both online and offline mode is the main focus of this system. The Internet based automation is made possible by the use of PLCs (Programmable Logic Controllers), SCADA (Supervisory control and Data Acquisition), VPN (Virtual Private Networks) and other network elements. The system is developed using SCADA software, PLC programs for controlling the real-time process and VBA / front page scripts for management information system. As a result the system will be more secured with the use of XML encoding and the data is protected by using only VPN via GSM for connection between the server and client and the individual monitoring device. The Reporting of the real-time data corresponding to the process plants can therefore be of great use for future analysis as well as for the Management level Information Systems.

This paper provides the analysis of Multicell converter at different levels which decreases the THD with increase in levels. This topology called SMC (Stacked Multicell Converter) consists of a hybrid association of commutation cell making possible to share the voltage constraint on several switches, and also to improve the output waveforms of the converter in terms of number of levels and switching frequency. PWM technique is used to control the rms voltage at the output. A closed loop control is proposed using MATLAB Fuzzy Logic Toolbox, to control the rms voltage at the output. A complete fuzzy inference process to control the converter is shown. The Fuzzy Controller for 3×2 and 5×2 multicell converter is compared and it has been found that 5×2 multcell converter has good voltage constraint sharing feature than its 3×2 counterpart with reduced number of switches.

We have demonstrated a 0.1-1.8 GHz, 100 W GaN HEMT power amplifier module with 11 dB gain, 94-142 W CW output power and 40.6-74.0 % drain efficiency over the band. The power amplifier module uses broadband low loss coaxial baluns to combine four 30 W broadband lossy matched GaN HEMT PAs on a 2 x 2 inch compact PCB. The individual PAs are fully matched to 50 Ohms and obtains 23.6-30.9 W with 44.5-63.7 % drain efficiency over the band. The packaged amplifiers contain a GaN on SiC device operating at 50 V drain voltage with a GaAs integrated passive matching circuitry. These amplifiers are targeted for use in multi-band multi-standard communication systems and for instrumentation applications.

To monitor and diagnose bottlenecks on network paths used for large-scale data transfers, there is an increasing trend to deploy measurement frameworks such as perfSONAR. These deployments use web-services to expose vast data archives of current and historic measurements, which can be queried across end-to-end multi-domain network paths. Consequently, there has arisen a need to develop automated techniques and intuitive tools that help analyze these measurements for detecting and notifying prominent network anomalies such as plateaus in both real-time and offline manner. In this paper, we present a dynamically adaptive plateau-detection (APD) scheme and its implementation in our “OnTimeDetect” tool to enable consumers of perfSONAR measurements within the data-intensive scientific communities in overcoming their existing limitations of network anomaly detection and notification. We empirically evaluate our APD scheme in terms of accuracy, agility and scalability by using measurement traces collected by OnTimeDetect tool from worldwide perfSONAR deployments in HPC communities.

We have demonstrated a decade bandwidth 100 W GaN HEMT power amplifier module with 15.5–18.6 dB gain, 104–121 W CW output power and 61.4–76.6 % drain efficiency over the 100–1000 MHz band. The 2 × 2 inch compact power amplifier module combines four 30 W lossy matched broadband GaN HEMT PAs packaged in a ceramic SO8 package. Each of the 4 devices is fully matched to 50 Ohms and obtains 30.8–35.7 W with 68.6–79.6 % drain efficiency over the band. The packaged amplifiers contain a GaN on SiC device operating at 48V drain voltage, alongside GaAs integrated passive matching circuitry. The four devices are combined using a broadband low loss coaxial balun. We believe this combination of output power, bandwidth and efficiency is the best reported to date. These amplifiers are targeted for use in multi-band public mobile radios and for instrumentation applications.

Remote Desktop Access (RDA) applications have become vital for users involved in tasks such as tele-commuting, distance learning, and remote instrumentation. To deliver optimum user Quality of Experience (QoE), existing RDA applications are “network-aware” i.e., they employ online encoding adaptation that is based on network Quality of Service (QoS) measurement between the client and server ends. In this paper, we propose and evaluate an online RDA encoding adaptation scheme that is “human-and-network aware” i.e., our novel adaptation considers Quality of Application (QoA) performance perceived by the user in addition to the network QoS measured by the application. Owing to our offline QoA performance modeling strategy that uses polynomial regression and bootstrap sampling, our scheme does not require input from actual users for the online encoding adaptation. Our performance validation results show that our proposed human-network-aware adaptation outperforms the network-aware adaptation in terms of user QoE for a wide-variety of degraded network QoS conditions.

We report a broadband lossy matched GaN on SiC HEMT power amplifier MMIC with 15dB gain, 0.5-2.5 GHz bandwidth, 9-13.6 W CW output power and 44.9-63.6% drain efficiency over the band. The amplifier operates from a 48V drain supply and is packaged in a ceramic SO8 package. These amplifiers are intended for use in wideband digital communication applications.

Follicular lymphoma (FL) is the second most common non-Hodgkins lymphoma in the United States. While the current diagnosis depends heavily on the review of H&E-stained tissues, additional sources of information such as IHC are occasionally needed. Matrix-assisted laser desorption/ionization mass spectrometry (MALDI-MS) can be used to generate protein profiles from localized tissue regions, thus making it possible to relate changes in tissue histology to the changes in the protein signature of the tissue. It may be possible to determine potential biomarkers that can indicate disease state and prognosis based on the protein profile. This research aims to combine two different but related types of data in order to develop a unique diagnosis methodology that can potentially improve the accuracy of diagnosis. Preliminary analysis has shown promising results for distinguishing intrafollicle regions from the mantle and follicle zones in normal tissue.

Because tests at Army Test and Evaluation Command (ATEC) ranges can often only be conducted under specific atmospheric conditions, climatologies of each range could be a very useful tool for long-range test planning. Such datasets can provide the probability density function of near-surface wind speed, percent cloud cover, temperature, precipitation, turbulence intensity, upper-atmospheric wind speed, etc., as a function of the month of the year, time of day, and location on the range. The STAR Institute with guidance from the Ohio Supercomputer Center is working on porting the Climate Four Dimensional Data Assimilation (CFDDA) technology developed by the National Center for Atmospheric Research to version 3 of the Weather and Research Forecast (WRF) model for use on systems within the Department of Defense High Performance Computing Modernization Prograf m. The fully parallelized WRF-CFDDA system uses data-assimilation by Newtonian relaxation, to generate a regional reanalysis that is consistent with both observations and model dynamics for every hour of the past 20 years, at fine scales (3 km grid) over the Dugway Proving Ground range.

Action potential generation and propagation is a critical parameter in the function of a neuronal network. The SCN1A voltage-gated sodium channel is an axonal protein crucial to action potential functionality. Here we have demonstrated the expression of a series of SCN1A genes in HEK 293 and primary neuronal cultures. The genes consist of a wildtype SCN1A as well as two point-mutation sequences. Expression was demonstrated using both immunocytochemistry and western blotting.

We have demonstrated a RLC matched GaN HEMT power amplifier with 12 dB gain, 0.05-2.0 GHz bandwidth, 8 W CW output power and 36.7-65.4% drain efficiency over the band. The amplifier is packaged in a ceramic S08 package and contains a GaN on SiC device operating at 28 V drain voltage, alongside GaAs integrated passive matching circuitry. A second circuit designed for 48 V operation and 15 W CW power over the same band, obtains over 20 W under pulsed condition with 10% duty cycle and 100 mus pulse width. CW measurements are pending after assembly in an alternate high power package. These amplifiers are suitable for use in wideband digital cellular infrastructure, handheld radios, and jamming applications.

This paper establishes the criteria to ensure stable operation of two-stage, bidirectional, isolated AC-DC converters. The bi-directional converter is analyzed in the context of a building block module (BBM) that enables a fully modular architecture for universal power flow conversion applications (AC-DC, DC-AC and DC-DC). The BBM consists of independently controlled AC-DC and isolated DC-DC converters that are cascaded for bidirectional power flow applications. The cascaded converters have different control objectives in different directions of power flow. This paper discusses methods to obtain the appropriate input and output impedances that determine stability in the context of bi-directional AC-DC power conversion. Design procedures to ensure stable operation with minimal interaction between the cascaded stages are presented. The analysis and design methods are validated through extensive simulation and hardware results.

We have developed 400 W pulsed output power GaN HEMT amplifiers with 2.9 – 3.5 GHz bandwidth. Operating the amplifier from a 65 V drain supply under pulsed operation with 10% duty cycle and 100μs pulse width obtains an output power in the range of 401 – 446 W over the band with a drain efficiency of 48 – 55%. The amplifier uses AlGaN/GaN HEMTs with a total device periphery of 44.4 mm and advanced source connected field plates for high breakdown voltage. These wideband high power amplifiers are suitable for use in pulsed radar applications.

This paper investigates certain novel switching sequences involving division of active vector time for space vector based pulsewidth modulation (PWM) generation for a voltage source inverter. This paper proposes two new sequences, and identifies all possible sequences, which result in the same average switching frequency as conventional space vector PWM (CSVPWM) at a given sampling frequency. This paper brings out a method for designing hybrid PWM techniques involving multiple sequences to reduce line current ripple. The three proposed hybrid PWM techniques (three-zone PWM, five-zone PWM and seven zone PWM) employ three, five and seven different sequences, respectively, in every sector. Each sequence is employed in a spatial region within the sector where it results in the lowest rms current ripple over the given sampling period. The proposed techniques lead to a significant reduction in THD over CSVPWM at high line voltages. The five-zone technique results in the lowest THD among real-time techniques with uniform sampling, while the seven-zone technique is the best among real-time techniques with twin sampling rates. The superior harmonic performance of the proposed techniques over CSVPWM and existing bus-clamping PWM techniques is established theoretically as well as experimentally.

This paper proposes a novel method called triangulation cut (Tcut) to improve upon current color image segmentation techniques. Tcut utilizes constrained delaunay triangulation, scale based tuning and graph spectral segmentation. Tcut approach has superior computational and memory efficiency over Normalized Cuts (Ncut). In addition, it avoids over- segmentation of large homogeneous regions and it groups spatially discontiguous but similar regions in the same segment. This results in an accurate estimate of the number of perceivable regions present in the image as compared to that of Ncut. Application of Tcut on variety of images have yielded promising results.

We report an efficient 250 W GaN HEMT power amplifier with 2.1 -2.5 GHz bandwidth. The amplifier employs AlGaN/GaN HEMTs with advanced source connected field plates, which are suitable for 48 V operation. The package combines two 22.2 mm periphery devices to obtain 54.0 dBm output power at 2.14 GHz and 54.6 dBm at 2.5 GHz, under pulsed condition with 10% duty cycle and 20mus pulse width. To our knowledge this is one of the widest bandwidth reported at this power level and frequency. These amplifiers are targeted for wideband digital cellular infrastructure; satellite communication, avionics and ISM band applications.