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A description is given of two test generation methods for sequential logic circuits. One method, called the 9ED method, is based on a path sensitization technique and is effective for asynchronous sequential circuits. The other methods, called the 4SP method, is also based on the path sensitization technique and is effective for sequential circuits with a design-for-testability (DFT) structure. The capabilities of these methods are examined with regard to the benchmark circuits prepared for ISCAS'89. The experimental results verified the effectiveness of the 4SP method for these circuits. >

This work presents an approach to the test generation for synchronous sequential circuits. This approach utilizes an extended logic simulation, called real-valued logic simulation, and solves the sequential test generation problem as a kind of optimization problem. The approach has the possibility of high speed test generation, because high speed processing techniques, such as, vector processing, parallel processing, and so on, can be efficiently applied to the most time-consuming part of this approach. Experimental results for ISCAS'89 benchmark sequential circuits also illustrate the eficiency of this approach.