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Owing to the existence of power-hungry clock networks, synchronous CNN accelerators are hard to achieve further low power consumption. In this paper, we propose a novel clockless asynchronous CNN processing element, replacing clock networks with asynchronous handshake signals. And then we construct a CNN computation array based on our PE and implement it in standard ASIC design flow. In addition, compared with the synchronous version that works at 200MHz frequency, our design can realize about 5.70× power consumption saving and 5.59× power-efficiency improvement when working at 196.0MHz equivalent frequency.

VGG-16 neural network is one of the most powerful artificial intelligence algorithms widely used in computer vision. There are many accelerators proposed for VGG-16 to obtain high energy efficiency but ignoring the existence of the power-hungry clock network. In this paper, we proposed an asynchronous convolution process engine for VGG-16 whose multiplication and accumulation (MAC) are clock-free asynchronous circuits. We also proposed a novel synchronous and asynchronous interface to solve the problem of setup time and hold time violations that easily occur when synchronous and asynchronous circuits are combined. The whole design was implemented in the 4Onm process. Experimental results show that compared with the synchronous version design, our asynchronous convolution process engine can achieve a 1.5x improvement in energy efficiency.