Search

The effects of Zr composition on the crystallization behaviors and reliability characteristics of atomic-layer-deposited \Hf1-x\Zrx\Oy \ (\0 \leq x \leq \1) gate-dielectric films are examined. n-Channel metal–oxide–semiconductor field-effect transistor (nMOSFET) devices with \ZrO2 gate dielectrics showed a much smaller V \rm th shift under the positive bias stress compared with the same device with \HfO2 gate dielectrics. The impact of Zr composition on the crystallization temperature, crystalline phases, and surface morphology of \Hf1-x\Zrx\Oy films is studied. As the Zr composition in the \Hf1-x\Zrx\Oy films increased, the reduction of crystallization temperature and the transformation from a monoclinic to a tetragonal phase were observed. The grain size of the crystallized \ZrO2 film is much smaller than that of crystallized \HfO2. The flatband voltage (Vfb) shift under positive gate-bias stress in p-channel MOS capacitor (pMOSCAP) devices show a similar trend to the Vth shift in nMOSFET devices. In addition, the annealed \ZrO2 films show a large reduction in the Vfb shift under the positive bias stress compared with as-deposited \ZrO2 in pMOSCAP devices. The improved bias-temperature-instability characteristics of \ZrO2 compared with that of \HfO2 is related to the smaller grain size of crystallized \ZrO2. [ABSTRACT FROM AUTHOR]

This letter examines the turn-around effect of a threshold voltage (Vth) shift of an n-type transistor with atomic-layer-deposited \HfOx\Ny gate dielectrics under a positive gate bias. Vth shifted to the positive voltage direction during the first second due to electron trapping at the preexisting trap sites in the gate dielectrics, which then shifted to the negative voltage direction. This turn-around effect was attributed to hole trapping originating from the generation of electron–hole pairs by the surface plasmon or impact ionization. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI) in MOSFETs with high-dielectric-constant (k) gate dielectrics has been investigated using a novel pulse NBTI measurement technique. This technique enabled the separation of the contribution of interface states (Nit) from that of oxide traps (Not) to NBTI behavior by varying the measurement time (tm) and the delay time (tR). The technique was demonstrated on devices fabricated with different postdeposition annealing (PDA) conditions. It was found that, regardless of the PDA condition, the Not in high-k dielectric was more responsible for the NBTI behavior than the Nit, but the contribution of Nit to NBTI increased as the stress continued because the generation rate of Nit was higher than that of Not. [ABSTRACT FROM AUTHOR]