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Gait analysis is one of the most basic methods for assessing a patient’s biopsychological status. Doctors can distinguish people with mental and neurological disorders by monitoring their gait. To perform gait analysis in a more quantitative and accurate manner, many studies have used inertial measurement units (IMUs), cameras and ground reaction force platforms. However, conventional gait analysis requires sensors to be attached to the subject’s body, and some of them are cost prohibitive. Currently, studies of noncontact gait analysis using radar sensors are being performed. Such studies have successfully measured several gait parameters associated with the noncontact method but have been unable to distinguish between individual legs. In this study, we proposed a method for noncontact gait analysis with a treadmill that could separate the left and right legs using multi-input and multi-output frequency-modulated continuous-wave (MIMO FMCW) radar. By recognizing two legs in a range-Doppler map and estimating their angles, ranges and velocities, the gait parameters of the individual legs could be identified. We performed experiments with 15 participants in 4 scenarios (walking, running, left leg limping, right leg limping) and compared gait parameters obtained using FMCW radar and IMUs. The gait parameter measurements were validated using the intraclass correlation value, and they showed excellent agreement except for flight time. Moreover, a parameter was identified that can accurately detect gait asymmetry, and its sensitivity (0.83) and specificity (1.00) were validated. Our future research will analyze not only feet movement but also arm movement so that it can be further applied to the medical field.

A high-precision DC measurement read-out integrated circuit (ROIC) is implemented from a low-noise capacitively-coupled chopper instrumentation amplifier (CCIA) followed by a high-resolution incremental discrete- time delta-sigma modulator (DTΔΣΜ) analog-to-digital converter (ADC). In this paper, a doubled sampling-time (DST) incremental DTΔΣΜ is proposed to reduce CCIA's bandwidth. Through the proposed technique, the power consumption of the traditionally power-hungry IA is halved, while the desired system specifications such as output data rate (ODR) and effective resolution (ER) are maintained. Implemented in a standard 0.13-µm CMOS process, the ROIC's effective resolution is 21.0 bit at gain 1 and that of 19.8 bit at gain 64. The analog part draws only 114.4 μA from 3-V supply.

In this paper, we propose a novel sequential compression method for the coefficient look-up table (LUT) for compensation of display panel defects. First, the regression LUT coefficient data for defect compensation is rearranged as the display ratio. It is split and compressed into sub-blocks to utilize the correlation of the rearranged data. Then, to further increase the compression ratio, the initially compressed data is compressed again through the differential coding-based compression. In the performance evaluation, the proposed method has the same loss as the existing compression method, while increasing the compression ratio of up to 46.9%.

A switched-capacitor (SC) DC-DC boost converter suitable for energy harvesting in IoT sensor systems with varying harvesting source and battery voltages is presented in this paper. Unlike the conventional multi-staged SC DC-DC converters, where efficiency is optimized only for a few topology-dependent conversion ratios, soft-charging-based SC conversion is adopted to achieve conversion-ratio-insensitive high efficiency. With soft-charging flying capacitors with small voltage steps, charge redistribution loss is minimized and evenly high conversion efficiency can be achieved for a wide range of input and output voltages. The proposed converter exhibited evenly high efficiency by achieving a peak efficiency of 85.3% and an average efficiency of 83.6% for generating regulated 1.8V output from a wide range of input voltages (0.9-1.8V). It also achieved a peak efficiency of 88.9% and an average efficiency of 87.6% for harvesting energy from a 1.2V source with a wide battery voltage range (3.0-4.2V).

Wind energy is considered as one of the most promising renewable energy sources due to its abundance and the high energy conversion efficiency of a wind turbine. Because wind flow is complex and highly variable, accurately predicting wind turbine responses such as power and loads speed is challenging. These responses are generally computed by computational wind turbine analysis tools that uses a wind flow as an input. In this study, we propose a machine learning approach to predict wind turbine responses using wind flow data as a direct input. Specifically, we use Multi-Tasks Convolutional Long Short-Term Memory Network to simultaneously predict the energy output and structural load from the target wind turbine while modeling the spatio-temporal structure of the input wind flow. The simulation experiment shows that the proposed model predicts the both outputs within a 5% error.

We present a novel systematic design framework for general under-actuated tendon-driven (UATD) robotic systems to exhibit desired behaviors both during the free motion and the contact task. For this, we propose stiffness decomposition, which enables us to completely decompose the configuration space of the UATD robotic systems into the actuated space (with full actuation via active tendons) and the un-actuated space (with no actuation, only with passive compliance and contact wrench). The behavior in the actuated space is then fully-controllable, thus, the attainment of the desired behaviors, particularly those during the contact task, hinges upon that in the un-actuated space. For this, relying on the stiffness decomposition, we optimize the design parameters (e.g., tendon routing, pulley radius, passive compliance, etc.) to ensure the deformation in the un-actuated space as directional (e.g., for adaptive grasping) and minimized (e.g., pushing with posture maintained) for different contact wrench sets as possible, while also rendering the free motion to be as compliant and backdrivable as possible. The presented framework is then applied to design a UATD robotic finger and experimentally verified with the robot able to mimic the behavior of human index finger both during the free motion and pinch-pushing.

With the growth of wearable devices, such as smart watches and smart glasses, there is an increasing demand for lower power dissipation, to achieve longer battery life with limited battery capacity. Nevertheless, memory bandwidth needs to increase to support high-resolution graphic engines. Since most wearable devices are event driven, they consume a bulk of power in standby mode. Therefore, it is crictical to reduce standby-mode power, as well as improve active-mode power efficiency. However, DRAM's periodic self-refresh, critical for data retention, imposes a lower bound on standby-mode power. This paper presents a 2Gb LPDDR4 SDRAM with 0.15mW standby mode power, which is 66% lower than the standby power for a memory of the same density. The proposed memory also achieves a bandwidth of 3.733Gb/s/pin. To extremely reduce standby mode power, an in-DRAM error-correction-code (ECC) engine is used for self-refresh current reduction. Intensive power gating in deep-power-down (DPD) mode, a temperature controlled internal power generator and an aggressively increased gate length is also used to reduce leakage current. In addition, active-mode power efficiency is improved by using a dual-page-size scheme.

An on-the-fly self-healing device is experimentally demonstrated for sustainability of space electronics. A high temperature, which is generated by Joule heating in a gate electrode, provides an on-chip annealing of damages induced by ionizing radiation, hot carrier, and tunneling stress. With the self-healing process, a highly scaled silicon nanowire gate-all-around field-effect transistor shows improved long-term reliability in a logic transistor, floating body DRAM, and charge-trap Flash memory, respectively. A thermally isolated gate structure is proposed to enhance the self-healing effect.

Fully wrap-gated carbon nanotube (CNT) transistors with vertically suspended (VS) semiconducting single-walled CNTs, purified up to 99.9%, are demonstrated for the first time. Without a sacrifice of scalability, remarkably enhanced gate controllability and charge transport capabilities were achieved due to the geometrical advantage of the gate-all-around (GAA) structure with multiple channels. The VS channels were formed with the aid of a silicon-processed vertically integrated nanowire frame, offering high completeness and compatibility with silicon processes. This approach will increase the applicability of CNTs toward high-performance emerging materials.

Photovoltaic (PV) model can be a viable alternative to the conventional look-up-table as an accurate and versatile solar array simulator (SAS) engine. In PV model-based SAS, PV model has a critical role to generate appropriate I-V characteristic of the PV panel under rapidly varying temperature and irradiation, and its calculation speed as well as accuracy are key performances. In this paper, a novel algorithm that is suitable for such a SAS engine is proposed. The suggested method adopts conjugate gradient optimization to extract PV model parameters from the changing conditions and to reconstruct the exact I-V curve very rapidly. For the verification, the proposed algorithm is compared with conventional ones which have been widely used in the PV model extraction. As a result, the proposed model shows superior calculation speed with good accuracy.

A heterogeneous multicore processor is proposed to accelerate advanced driver assistance system (ADAS). To enable a real-time operation of ADAS functions with 720p stereo video stream, multiple granualrity parallel SIMD/MIMD architecture is proposed with precise visual attention and high throughput network-on-chip to reduce computation cost and network congestion, respectively. In addition, it employs a data resource management processor to control workload-prediction dynamic voltage and frequency scaling to reduce power consumption. As a result, the proposed SoC ahcieves 862GOPS/W energy efficiency and 31.4GOPS/mm2 area efficiency, which are 53% and 75% improvement over the state-of-the-art ADAS processor, respectively.

Wearable head-mounted display (HMD) smart devices are emerging as a smartphone substitute due to their ease of use and suitability for advanced applications, such as gaming and augmented reality (AR) [1–2]. Most current HMD systems suffer from: 1) a lack of rich user interfaces, 2) short battery life, and 3) heavy weight. Although current HMDs (e.g. Google Glass) use a touch panel and voice commands as the interface, such interfaces are solely smartphone extensions and are not optimized for HMD. Recently, gaze was proposed for an HMD user interface [2], but gaze cannot realize a natural user interface and experience (UI/UX), due to its limited interactivity and lengthy gaze-calibration time (several minutes). In this paper, as shown in Fig. 14.1.1, gesture and speech recognition are proposed as natural UI/UX, based on: 1) speech pre-processing: 2-channel ICA (independent component analysis), speech selection, and noise cancellation and 2) gesture pre-processing: depth/color-map generation, hand detection, hand segmentation, and noise cancellation. This paper presents a low-power natural UI/UX processor with an embedded deep-learning core (NINEX) to provide wearable AR for HMD users without calibration. Moreover, it provides higher recognition accuracy than previous work [3].

An energy-efficient Deep Neural Network (DNN) processor is proposed for high-speed Visual Attention (VA) engine in a mobile vision SoC. The proposed embedded DNN realizes VA to rapidly find ROI tiles of potential target objects reducing ∼70% of recognition workloads of vision processor. Compared to previous VA, the DNN VA reduces execution time by 90%, which results in 73.4% overall OR time reduction. Highly-parallel 200-way PEs are implemented in the DNN processor with 2D image sliding architecture, and only 3ms of DNN VA latency can be obtained. Also, the dual-mode PE configuration is proposed for both DNN and multi-layer-perceptron (MLP) to share same hardware for high energy efficiency. As a result, the proposed work achieves only 1.9nJ/pixel energy efficiency which is 7.7x smaller than state-of-the-art VA accelerator.

Electric field-coupled wireless power transmission utilizes the electric field applied between the physically separated metal plates. In this application, how to provide the regulated output voltage through the resonant LC link are challenging task. In this paper, analysis and control design of such system are investigated. Following small signal and high Q approximation, transfer function of the overall power stage including the transmitter and receiver circuit is extracted and the control loop is designed in the frequency domain. The theoretical results are verified by PSIM simulation for a 10V/0.5A prototype system.

This paper investigates a novel tolerance design method for a resistive light-emitting-diode (LED) driver with multi-string configuration in mass production. Considering a trade-off among the current uniformity, the current accuracy in LEDs, and the loss dissipation in the driver circuit, a bus voltage and a series resistor are identified as two design parameters regardless of production spreads both in the LED string voltage and in the ballast resistance. By combining discrete optimization technique with Monte-Carlo method, this paper proposes an effective algorithm to design the circuit parameters. Comparison with the conventional design by simulation and hardware tests shows that the suggested scheme provides more reliability and flexibility in practical situation. Moreover, utilizing only datasheet values eliminates the need for I-V curve extraction in the design process.

This paper presents an improved parameter extraction algorithm for photovoltaic (PV) panels based on only datasheet value, which is very useful in the development phase of power conditioning system (PCS). In order to increase the accuracy of PV circuit model especially in the maximum power point (MPP), optimization method with objective function incorporating only the MPP conditions was suggested to obtain the circuit parameters in the single diode model. Pattern search optimization was adopted to implement the algorithm and search region with initial value was also discussed. The measurement data from crystalline PV array showed that the proposed algorithm improved the accuracy near the MPP in comparison with conventional methods. Furthermore, the suggested method provides more uniform and fast way of parameter extraction which is less dependent on power rating of panel and user's skill.

This paper demonstrates a 12.5-Gb/s complete transceiver with near-ground and voltage-mode signaling. The output stage of the transmitter has two types of equalization methods: 2-tap FIR, AC-coupled equalization. The receiver equalizes the attenuation of the cable with a continuous time linear equalizer which includes a level-up shifter for receiving near-ground input signal. A dual-loop clock and data recovery circuit using a bang-bang phase detector is implemented for a receiver clock generation. The test-chips are fabricated in a 45-nm CMOS technology, and successfully perform data communication through -27 dB loss video cables. The entire transmitter and receiver test-chips respectively consume 92 mW and 138 mW from a 1.2 V supply while operating at 12.5 Gb/s.

A Vocabulary Forest-based object matching processor is proposed to speed up the feature matching stage for the object recognition system with high accuracy. Adopting Reusable-Vocabulary Tree architecture and hardware sharing technique reduces area, as well as adopting propagate-and-compute-array architecture in the combiner and external database elimination enhances the matching speed more than 16x compared to Approximate Nearest Neighbor searching processors. The proposed Vocabulary Forest processor, implemented in 65nm CMOS process, achieves 2.07M-vec/s throughput and 13.3nJ/vector energy efficiency, and successfully matches 100 objects with 95.7% matching accuracy.

A 36 Heterogeneous multicore processor is proposed to accelerate recognition-based markerless augmented reality. To enable a real-time operation of the proposed augmented reality, task-level pipelined multicore architecture with DLP/TLP optimized SIMD processing elements is implemented. In addition, the multicore employs a congestion-aware network-on-chip scheduler for 2D-mesh network-on-chip to support massive internal data transaction caused by task-level pipeline. As a result, it achieves 1.22TOPS peak performance and 1.57TOPS/W energy-efficiency, which are 88% and 76% improvement over a state-of-the-art augmented reality processor, for 30fps 720p test input video.

This paper presents the design of surface mounted brushless DC motor for personal electric mobility system. In order to get a high torque and performance at low dc link voltage, characteristic of according to ratio of stator pole and rotor pole, rotor type, turn of winding is compared. The designed prototype drive system is verified by simulation and experimental test.

High-resolution image offers more details compared to low-resolution image and consequently improves the accuracy of object recognition. However, higher resolution requires a costly hardware for large image sensor, or computation for additional signal processing. In this paper, we present a high-throughput super resolution processor for high-resolution object recognition. In order to perform super resolution with the real-time object recognition SoC, the algorithm-specific hardware is proposed with 2-D image cache and locality-sensitive hashing accelerator for high-throughput image fetching and searching. As a result, the proposed super resolution processor generates up to 16× higher resolution images with 3,125 fps throughput and 2.0 nJ/pixel energy efficiency, enabling high-resolution pre-processing for real-time object recognition.

In this paper, we propose a 60fps cortical vision processor modeling a hierarchical object classification model (HMAX) based on spatio-temporality in video stream. It is hard to implement a real-time hardware for HMAX operation due to its high computational cost from 2-D template matching. Three components are proposed with our improved algorithms. Class Refinement Structure (CRS) dramatically reduces a dimension of HMAX descriptors by 97.01% compared to the previous works by exploiting spatio-temporal features in video action recognition. Spatio-Temporal Memory Structure (STMS) adopts spatially adaptive window technique, and it reduces the required on-chip data bandwidth and computations per a template in S2 stage. In addition, a dual image buffer structure also reduces the required off-chip network bandwidth for processing complex hierarchical stages and numerous image spaces. As a result, the 10.8 GOPS cortical vision processor implemented in 0.13μm CMOS process achieves 60frames/sec performances for 256×256 video inputs at 200MHz operating frequency.

A scale-space processor with two-dimensional cache is proposed to achieve real-time object recognition in HD 720p images. Scale-space is the most commonly used concept to achieve scale-invariant property in object recognition, however its high computational cost makes it hard to implement a realtime object recognition processor. We employ hierarchical convolution unit (HCU) which computes multiple pixels in a single cycle with various kernel sizes. In addition, two-dimensional cache (T-Cache) supports accessing vertically consecutive data from any image window size with reduced area. A pre-fetch controller for the proposed cache improves the hit rate by exploiting the sequential access pattern of convolution tasks. As a result, the scale-space processor implemented in a 0.13μm CMOS technology achieves 34.1fps on a HD 720p image while consuming peak power of 84.5mW.

We propose an analog Radial-Basis-Function (RBF) circuit that generates 4 different types of RBFs, which are spline, Gaussian, multi-quadratic, and log-like spline curves. Moreover, the proposed RBF circuit is designed to have high tunability on centers, heights, and widths. The proposed RBF circuit is also robust to both temperature variation (-37~87□C) and supply voltage variation (1~2V). The sum of area and power consumption of each RBF from 3 different previous works is 13, 622μm2 and 121μW, respectively. On the other hand, the proposed circuit occupies only 1,050μm2 and consumes 10.5μW which are only 13% and 11.5%, respectively. For its verification, an analog/digital mixed-mode RBF Neural Network (RBFNN) classifier is designed which adopted the proposed RBF circuit.

This paper presents a dynamic resource controller (DRC) with network-on-chip (NoC) for an energy-efficient multi-core processor. A total 21 cores in 5 local voltage/frequency islands (VFIs) can be controlled by dynamic resource management (DRM) with the proposed workload-utilization product based prediction model. And a 0.31mm2 compact 8×8 NoC switch is designed to reduce unnecessary ~24% power dissipation of each VFI by adopting DVFS and the bandwidth regulation. As a result, thanks to 42% reduction of power-delay product by DRM-based NoC architecture, the 32 mm2 multi-core processor, fabricated 0.13μm CMOS process, achieves 10.5nJ/pixel efficiency, 3.54x improvement compared to state-of-the-art object recognition processors.

An on-chip serial-link scheme incorporating an interleaved voltage-mode driver, interleaved samplers and an optimally resistively terminated transmission line, enables an energy-efficient very-high-speed long-range data communication. The link is more than twice as fast and more than twice as energy efficient as the fastest reported on-chip link, yet has more than triple the communication range. A 10mm prototype link achieves a data rate of 20Gb/s with an energy consumption of 1.36pJ/b and a measured BER better than 10−11. A 10Gb/s prototype achieves an energy efficiency of 680fJ/b with a measured BER of less than 10−13.

A simultaneous multithreading multicore processor is proposed to accelerate object recognition for 720p HD video streams. The multithreading architecture with Q-learning based dynamic resource management enables concurrent processing of 8 region-of-interests with 5-stage fine grained recognition pipeline outperforming previous object recognition processors with 342GOPS computing power. In addition, the dynamic resource management contributes to increase of energy efficiency by applying the on-line learning DVFS and dynamic tile allocation based on task variance and hardware utilization to achieve 9.6mJ/frame with 1280×720 pixel image. It achieves 2.72× throughput and 3.7× energy efficiency compared to previous recognition processors.

A passively assembled four-channel OSA module has been accomplished exploiting an injection molded plastic optics structure in conjunction with a ribbon POF. It readily afforded to deliver a full HD (1080p) HDMI video data.

Coarse WDM based short-reach OSA modules were demonstrated by taking advantage of a passive alignment scheme. They were used to build an optical HDMI cable, affording to efficiently deliver 1080p HDMI video/audio data.

A hybrid radix-4/-8 multiplier is proposed for portable multimedia applications that demand high speed and low energy operation. Depending on the input pattern, the multiplier operates in the radix-8 mode in 56% of the input cases for low power, but reverts to the radix-4 mode in 44% of the slower input cases for high speed. For this, a mode detection circuit determines the mode signal from the input operand in just 2 gate delays. Based on the mode signal, the radix-4/-8 dual Booth encoder generates encoding signals in a hardware efficient way. Moreover, the carry save adder block is selectively activated to reduce power consumption. Compared to a conventional radix-4 multiplier, the proposed hybrid multiplier architecture consumes 33.5% less power at the expense of just 3.3% additional propagation delay, resulting in 31.3% less energy per operation.

Artificial intelligence (AI) functions are becoming important in smartphones, portable game consoles, and robots for such intelligent applications as object detection, recognition, and human-computer interfaces (HCI). Most of these functions are realized in software with neural networks (NN) and fuzzy systems (FS), but due to power and speed limitations, a hardware solution is needed. For example, software implementations of object-recognition algorithms like SIFT consume ∼10W and ∼1s delay even on a 2.4GHz PC CPU. Previously, GPGPUs or ASICs were used to realize AI functions [1–2]. But GPGPUs just emulate NN/FS with many processing elements to speed up the software, while still consuming a large amount of power. On the other hand, low-power ASICs have been mostly dedicated stand-alone processors, not suitable to be ported into many different systems [2].

A vector matching processor with memory bandwidth optimizations is proposed to achieve real-time matching of 128 dimensional SIFT features extracted from VGA video. The main bottleneck of feature-vector matching is the off-chip database access. We employ the locality sensitive hashing (LSH) algorithm which reduces the number of database comparisons required to match each query. In addition, database compression using Huffman coding increases the effective external bandwidth. Dedicated parallel Huffman decoder hardware ensures fast decompression of the database. A flexible query re-ordering buffer exploits overlapping accesses between queries by enabling out-of-order query processing to minimize redundant off-chip access. As a result, the 76.8 GOPS feature matching processor implemented in a 0.13um CMOS process achieves 43200 queries/second on a 100 object database while consuming peak power of 92mW.

A passively aligned short-reach optical sub-assembly module has been built, taking advantage of a filter free coarse WDM incorporating VCSELs at 780 and 850 nm.

Balancing the execution times of concurrent tasks in a multi-core processor is critical to achieving good performance scaling with increasing core count. However, this is difficult when the tasks' execution times are not known in advance. In this work, we propose an intelligent Network-on-Chip that performs bandwidth regulation using weighted round robin packet arbitration to balance the execution times of 4 Feature Extraction Clusters whose workloads vary depending on the input content. A neuro-fuzzy inference block, named the Intelligent Inference Engine, predicts the workload of each FEC, and assigns a priority weight to each FEC channel. As a result, 34% reduction in synchronization overhead due to unbalanced execution time was achieved, and the overall execution time was reduced by 11.5%.

High-quality CuInSe 2 nanoparticles have been prepared by the solution phase synthesis procedure utilizing copper acetate or cuprous chloride as the Cu-precursor, indium chloride as the In-precursor and selenium powder as Se precursor, respectively. The synthesis process was optimized to grow 20 to 150 nm sized nanostructures of CuInSe 2 , and the Cu to In ratio as well as the kind of Cu-precursor used was found to be most important in determining the structure and property of the nanostructures. The synthesized nanostructures were characterized by TEM (transmission electron microscopy), XRD (X-ray diffraction), PL (photoluminescence) and micro-Raman spectroscopy, and detailed microstructural analyses of synthesized samples were also carried out by selective area electron diffraction (SAED) and high-resolution transmission electron microscopy (HRTEM).

An intelligent inference engine (IIE) is proposed as a controller for low power high speed robust object recognition processor. It contains analog digital mixed mode neuro-fuzzy circuits for the on-line learning to increase attention efficiency. It is implemented in 0.13um CMOS process and achieves 1.2mW power consumption with 94% average classification accuracy within 1us operation. The 0.765mm2 IIE achieves 76% attention efficiency, and reduces power and processing delay of the 50mm2 recognition processor by up to 37% and 28%, respectively, with 96 % recognition accuracy.