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Laser Marking is a very common part of many manufacturing processes usually performed at the last stages of production lines after the packaging of goods. The speed of production lines are key determinants of the output capacity of many industries, but their scalability could be hindered by some fundamental limits of current laser marking technologies. In this paper, we review related technologies, their limiting factors, and analyze how future systems could overcome them.

Neural Architecture Search (NAS), which allows for automatically developing neural networks, has been mostly devoted to performance on a single metric, usually accuracy. New approaches have added more objectives, such as model size, in order to find networks suitable for resource-constrained platforms. SpArSe [1] is a multi-objective Bayesian optimization framework for automatically developing image classification convolutional neural networks (CNNs) for micro-controller units (MCUs). In this work, we first implement SpArSe and modify it to reduce search time, obtaining similar results regarding accuracy, model size, and maximum working memory but in less optimization time. Moreover, we extend the search space to include recurrent neural networks (RNNs) and add an inference latency objective for time-constrained tasks. Finally, we test our implementation in a gesture recognition task obtaining better results than previous manually tuned approaches for size and performance metrics, which validates the approach and its utility.

Capacitive sensing offers new possibilities for HMI product development. Its short range of interaction entails robustness against environmental noise and its flexibility for integration makes it a genuine technology for embedded systems. In the automotive context, capacitive sensing is explicitly devoted to driver interaction with car functionalities. However, the increasing complexity of captured signals and related interaction procedures impose severe difficulties for a classic modelling approach. Neural networks have demonstrated unbeatable performance in tasks with abundant data. Specifically, recurrent neural networks (RNNs) show excellent performance for tasks with inherent temporal structure. In this article, we develop a capacitive-sensing module that includes RNN-based dynamic gesture recognition, which has a suitable implementation size for embedded automotive applications.

In this paper we present a novel method to print paper and cardboard without ink. The method is based on the carbonization of paper by a combination of lasers working on different wavelengths. A prove of concept system is created based on combining existing commercial systems to demonstrate the viability of the method. The results show that no debris is generated and the quality of the mark is superior in terms of contrast and resolution with previously known methods.

This paper presents two main contributions toward efficient VLSI circuits mapped with simple cells: (1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and (2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. We show that efficient implementations in terms of inverter count, transistor count, area, power and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while (i) optimizing the number of added inverters; and (ii) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation and delay up to 48%, 4%, 8%, 14%, and 16%, respectively.

Pedestrian detection is a vital function of the emerging autonomous vehicle industry. HOG is widely used as the feature extractor for pedestrian detection thanks to its high accuracy despite the fact that it is computationally expensive. Hardware accelerators using GPUs or FPGAs are used in several proposals to address its real-time execution. There is always a trade-off between real-time processing, energy efficiency and accuracy in the existing solutions. In this paper, we present a pipelined implementation of HOG feature extraction on a low-cost Cyclone V SoC FPGA platform. The design is provides a latency of 4ms for every 640×480 input frame, which corresponds to 250fps. The whole detection system reduces the power consumption by 53.3% and 96% compared with state of the art FPGA and GPU alternatives.

We present a new Placement and Routing (P&R) strategy for implementing digital Organic/Flexible/Printed Electronics (PE) circuits based on an Inkjet-configurable Gate Array (IGA) design style together with digital printing personalization.

We perform clustering over the Product Reactions Cards in order to group the terms in 8 groups and 41 subgroups. A card sorting exercise among software engineers and UX practitioners was performed in order to achieve this. We present a preliminary case study using this classification with a retailing application in order to see the difference in connotations that result introducing stereoscopic depth to the GUI.

While silicon based technologies are evolving towards very advanced nanometric nodes (≤ 20nm), the emerging thin-flexible-organic-large-area electronics (a.k.a. printed electronics, PE) based on flexible substrates and functional inks are starting again the history of microelectronics at technology and device levels trying to grow up to applications looking at the silicon path but far away from its costs and performances.

In this article, we present a drawing toolkit developed to create stereoscopic side-by-side 3D stimuli. The toolkit is based in the HTML5 canvas element and drawing is achieved using intermediate stereo scripting methods that correspond to the ‘2d’ context of the canvas. We include performance marks of the toolkit running on desktop and mobile browsers. Also, a discussion of how the tool is used for implementing a stereo 3D UI is specified.

This paper presents a top-down approach for the design process of digital Application Specific Printed Electronics (PE) Circuits (ASPECs); from functionality specification at circuit level (i.e. HDL), through the optimization of combinational circuitry (represented by their logical equations), according to the PMOS-based technology that will be used to build a set of Standard Cells (SC) or use a predesign Inkjet Gate Array (IGA), down to the Place and Route to get the final circuit layout. This process will use the technology coming from the Centre for Process Innovation (CPI). This methodology maps the existing ASIC one by updating design styles and cost functions. Thus, it is portable to different Printed Electronics processes, using state-of-the-art logic synthesis EDA/software tools being the main optimization goal the transistor count. Main reason is that printed electronics technologies show low density and not such high yield compared to traditional Silicon-based microelectronics. To illustrate this methodology, we use the design and implementation of the TicTacToe game to be implemented together with flexible textile pressure sensor and lighting.

Application Specific Printed Electronics Circuit (ASPEC), a circuit designed and customized for a special application rather than intended for general-purpose use, is the equivalent term for ASIC but for printed electronics. In this paper, we extend the printed electronics to ASPEC design by developing a standard cell library for CPI (center for Process Innovation) technology which substrate is flexible PEN(50 micron thickness), laminated to glass using the PDMS bounding process. Standard cells topology allows full automation of the layout design process using automated place and route tools. In addition, Standard cells significantly help speeding the circuit development time as the blocks can be synthesized from high level descriptions (Verflog, VHDL) using the library. The cell library is generated for two different types of Top-gate bottom contact Organic Thin Film Transistors (OTFTs): l)Inter-digitated OTFT, 2)Corbino OTFT. The pseudo ratioed pMOS lodic is used for the circuitry since only p-channel transistors are available. The developed library consists of 7 gates: 5 combinational gates (Inverter, NAND2, NAND3, NAND4, and XOR2) and 2 sequential gates (D flip flop and enable D flip flop) and a FEED cell. Glade layout editor and MaskEngineer 4.8.4 and AIMSpice simulator have been used to design the cells layout and simulate the cell circuits. Automatic extraction of electrical interconnections from layout has been done in order to enable layout versus schematic (LVS). Finally, Tic-Tac-Toe game using combinational circuit has been designed, fabricated and will be characterized to demonstrate the standard cell library.

This paper presents an investigation about the ideal composition of cell libraries to be used for digital Application Specific Printed Electronics Circuits (ASPECs). Printed/organic/flexible electronics is becoming more and more important over the last years, and it seems that the industry will continue growing as new possible applications arise, and the existing ones are being improved due to better designs and fabrication processes, even moving towards integrating logic circuitry together with sensors and actuators. This paper presents considerations for developing (ASPECs), trying to keep a similar approach to the typical ASIC procedures. The work presented herein adopted a cell-based design methodology addressed to printed electronics (PE) designs. Such methodology allows us to propose a design flow for PE similar to the VLSI design flow, comprising logic synthesis, mapping, placement, and routing. In order to evaluate different library compositions, a set of benchmark has been mapped with six different combinations of mapping tools and associated libraries. The obtained results show that a simple library composed of just three cells - either NAND2, NOR2 and inverters or NAND, NAND3 and inverters - performs very well in terms of transistor count. NAND gates are usually preferred options for ratioed PMOS-only design styles. Using a more complex cell library can produce reductions of around 25% in terms of transistor count, but produce increases of around 23% as well.

Multi-Processor Systems-on-a-chip (MPSoCs) are currently the most common implementation technique to build complex systems that provide high performance according to both timing and power restrictions for electronic systems. Both many-core (usually homogeneous multiprocessing) and multi-core (more often heterogeneous) require providing some complex parallel programming methods together with architectural exploration and performance analysis tools to get into an optimal solution. The concept of network-on-chip and programming model topics on multiprocessors system-on-chip world will be reviewed using some selected proposals to highlight the evolution of the implementation approaches. FPGAs are being used to prototype these complex systems since they provide a high degree of visibility of the system activity at different levels of abstraction. The emerging Reconfigurable Hardware devices allow the design of complex embedded systems combining soft-core processors and a mix of other IP cores. The reduced NRE costs compared to ASIC is a typical reason to choose FPGAs as a platform to implement some applications. But the continuous increase of capacity, and the flexibility offered by reconfigurable hardware, are also important reasons to select FPGAs in order to get good Time-to-Market and Time-in-Market values. Furthermore, and because of this existing infrastructure, FPGAs can provide multi-soft-core solutions are a viable suppose and interesting solutions for embedded systems that naturally appear after new general purpose platforms. These embedded systems are therefore oriented to specific purpose applications and need some additional trade-off between performance, flexibility and development time. FPGAs allows that, at a reasonable cost, we will have available many-soft-cores solutions so that they are expected to have some relevance for some future embedded systems. Then, in addition to the current soft-core SoC tools, some parallel programming methods and tools will be required as a part of the full system development process. Performance analysis tools have also to be updated taking into account specificities of parallel programming (most of them coming from the high performance computing community) has a critical part of the development process for parallel embedded applications. Meeting some real-time constraints is a critical issue when you want to get a desired performance. A basic review of the techniques used by the HPC community will be reviewed such as the post-mortem analysis of application traces, taking into account the resource limitations of the FPGA platforms for embedded systems. This review will include several techniques and some Hardware architectural support to be able to generate traces on multiprocessor systems based on FPGAs and use them to optimize the performance of the running applications. Finally, soft-cores allow an additional advantage due to the fact that one can easily add hardware acceleration or improve communications performance, as usual bottlenecks to reach performance constraints, by using ad-hoc solutions coming from the analysis of the system behavior at different levels of abstraction (from parallel programming down to node activities). QoS techniques, also added to some of the programming methods to dynamically cope with performance, will also be reviewed.

This paper reports on usage of Greek cross test structure to characterize geometry of inkjet printed electronics circuits. Geometric characteristics extracted from optical characterization can be correlated with electric measurements for square resistance in order to speed up the characterization processes. Design of inkjet printed Greek cross test structure should consider the ink coalescence and coffee ring effects.

This paper presents the design of a multi-processor system to control a Laser Marking machine. The use of multiple soft-core processors allows to independently control multiple heads that share a single laser beam. We show that with several design decisions we can increase the laser beam utilization factor up to 92%. Besides, we present a multi-soft-core architecture, a particular programming model, and how the system is extended to enable performance analysis.

The emergence of wearable intelligent textile systems with sensors and actuators nodes are integrated into user clothes. Emergency units can benefit from new technologies to improve their performance and security conditions when working exposed to risk situations. In firefighters case is a the system Bluetooth Low Energy (BLE) at 2.4GHz with a watch to show the thermal stress and, in case of exceed healthy level will trigger an alarm to warn the user. In this scenario the design and study of the working conditions of an antenna is a crucial issue for ensuring the communication capabilities of the the whole system. In this work paper we present the design, development and test of a miniature flexible antenna prepared to integrate in the uniforms maintaining the radiation properties although bend or warming. We will see how to minimize the size of the antenna with a antenna PIFA on a Polyethylene Terephtalate (PET) substrate.

Modern top of the line FPGAs can already host hundreds of simple soft-core processors. Because soft-cores often support floating point units through external interfaces this opens the door to explore the convenience for sharing the floating point units among a number of processors in many-soft-cores. We build two variants of a many-soft-core with 16 NIOSII cores to test if sharing the FPU gives an important area reduction and to test if the introduced time overhead is significant. We find out that area savings are a 30% of the non-shared FPU version for a 16 core system and that the overhead in clock cycles is almost inexistent for simple applications like matrix multiplication and below 2% for a parallel Mandelbrot application. However, if we consider the reduction of the maximum operational frequency that happens when the number of processors increase, we get that sharing among 8 processors is a very good option, and that it is not advisable to share among more than 12 processors because of the excessive time overhead

The number of resources available in the largest reconfigurable devices enables the synthesis of systems with more than 100 Soft-Core processors. Although a feasible and attainable option, few such systems have been built and few published works propose methods to create, program and optimize this kind of system. In this work we present a methodology that helps the designer to build Multi Processor System on Chip (MPSoC) systems based on Network on Chip (NoC) interconnection, and also to develop applications and to analyze their performance. In this methodology several tools have been combined such as SOPC builder from Altera, NoCMaker from UAB, and Vampir from GWT-TUD. As a result, a NoC-based MPSoC consisting of 16 NIOS II Soft-Core processors has been built and successfully tested with several applications.

A novel technique for the remote reading of chipless capacitive sensor Tags and one of its possible applications is presented. For this purpose, a frequency agile reader has been developed using Software Defined Radio (SDR) architectures, capable of scanning with high precision a frequency range given by an external user and extracting the resonant frequency of a Tag. The capacitive sensor Tag has been implemented on a plastic substrate using inkjet printing techniques. In order to demonstrate the feasibility of the technique, the reader analyzes the Tag's backscatter response and gets its resonant frequency in a case study of a moisture sensor application.

Inkjet printing is one of the most promising techniques that could potentially revolutionize large area and organic electronics fabrication. At the moment, technology is still under development and some problems remain to be solved. Only few applications have been demonstrated with enough performance to be moved to industrial level. In this paper we present the study of a potentially successful inkjet printing application: a Near Field Communication Antenna. In our work we characterized an inkjet printing process and developed an antenna design to evaluate its potential. Fabricated antenna was tested on NFC systems and final results lead us to conclude that NFC antennas are a potentially successful inkjet printing application.

The presence of new technologies on distance education generates a cloud of learning environments with high presence of multimedia contents and mobility capabilities. The widespread use of mobile technologies, digital TV and Internet enables ubiquitous learning environments that allow students to learn anywhere anytime. However, the diversity of computational and display capabilities of the current access devices (i.e. PC, mobile phones, set-top boxes) requires a smart content design methodology to reduce the development time. This paper aims to present the methodology followed to generate platform-independent interactive learning materials with high presence of multimedia resources and its deployment in different platforms. The methodology is shown taking the example of an interactive application to drive a seminar on the soldering process of complex BGA chip packages for building electronic systems. This content design process is shown from our platform-independent design level until its deployment in PC, TV and mobile platforms. This may help teachers and content creators in the generation of learning materials that are independent of the Learning Content Management System (LCMS) that serve it and the device used to access to it. Moreover, basic guidelines are given to generate the classroom materials through the same unified design process.

Embedded multimedia systems are expected to fully embrace the future many-core wave. As a consequence parallel programming is being revamped as the only way to exploit the power of coming chips. While waiting for them we try to extrapolate some lessons learned from current multi-cores to influence future architectures and programming methods. In this paper we investigate the parallelism and scalability of a JPEG image encoder, which is a typical embedded application, on several shared memory machines using the OpenMP programming framework. We identify the Huffman coding as the bottleneck that blocks the application from scaling above a 7x factor. We propose a strategy to parallelize the Huffman coding, which introduces a small degradation in some parts of the image, allowing to reach higher speedup factors. A factor of 18.8x has been reached in SGI Altix 4700 using 22 threads. Contrasting these results with some previous works using message passing architectures we consider that the use of OpenMP on top of shared memory architectures should be reconsidered for future chips in favor of message passing architectures and programming models.

Production and maintenance of interactive digital television (iTV) services can be a hard task due to the diversity of deployed digital television (DTV) platforms and the differences in terms of capabilities and functionalities between the receiver devices. The Digital Video Broadcasting (DVB) Portable Content Format (PCF) is a standard platform-independent service description which specifies the viewer experience in an iTV platform. It allows a unified authoring through a later transcoding to the final device. This paper proposes a workflow to produce and maintain platform-independent web-based iTV services from the application design level to the final deployed service through that standard. Moreover, this paper details the main characteristics of an implemented PCF to web-based platform transcoder, which can be applied to most IPTV and WebTV platforms.

Developing HW modules for standard platforms like PCs or embedded devices requires a complete system emulator availability to detect and fix bugs on developed HW, Operating Systems (OS) drivers and applications. This paper presents a set of plug-ins to an open-source CPU emulator that enables mixed simulations between platforms emulators and hardware (HW) modules described in SystemC. In this paper three plugins for QEMU are described: one for connecting TLM SystemC modules to any bus QEMU emulates, one for connecting SystemC to PCI bus for PC based platform and one plug-in for connecting SystemC to AMBA bus for ARM platforms. With this framework, it is possible to develop OS drivers at the same time HW is developed and final application tested running in this virtual platform.

Changing user scenarios demand wireless connectivity among different standards. As a result, reconfigurability is becoming a key issue in the design of future wireless terminals. In analog front-ends, reconfigurable components are very expensive in terms of design cost and area. Bandpass sampling and digital front-end solutions in general, move the ADC closer to the antenna, avoiding most of the reconfigurable analog hardware. We consider the extreme case of bandpass sampling at RF and analyze the ADC requirements for a multi-standard radio. Two different models, one based on cascade analysis and the other on time-domain simulations, are used with a representative set of emerging wireless standards to derive the ADC requirements: sampling frequency, resolution and clock jitter. This study shows that, with modest RF filtering, RF bandpass sampling will soon become a reality for low power terminals.

Optical character recognition systems are used extensively for document acquisition. This paper describes the architecture and implementation of a camera-based digit recognition system to be used by an automated meter-reading device (AMR). This application has very specific requirements that can let to an optimized application specific hardware design. In the presented architecture the meter image is acquired by a CMOS image sensor and processed and recognized by an FPGA in real time. The proposed method for digit recognition is based on an original application of sequence alignment algorithms. The system is prototyped in a low cost FPGA.

Simulating a NoC at the RTL level can be extremely complex, the simulation of a relatively small NoC, such as a 4 times 4 mesh, can involve observing thousands of wires on a standard HDL simulator. The facilities of JHDL to extend the simulator environment together with the possibility to fully analyze the runtime object model of the circuit offers a great opportunity to develop modules that address complex features like high level validation and performance evaluation. We present a developed tool that allows defining a NoC architecture models with some flexibility. Traffic generation processes described with high level language can be added to the model. Simulation can be used to validate the system operation on realistic conditions and get accurate values of expected performance

Developers of next generation Multi-Processor Systems-on-a-chip (MPSoC) silicon platforms used in multimedia mobile devices should design efficient systems for diverse execution time vs. energy consumption trade-offs for a given quality of service. By exploiting Dynamic Voltage and Frequency Scaling (DVFS) techniques we can obtain singular computational/power trades offs points and thus design energy efficient platforms. This paper presents a high level methodology to acquire an optimal set of working points for an MPEG-4 Single Profile (SP) Video encoder implementation. The flow starts from a MPEG-4 encoder described in C++ language which is translated to a SystemC hard/soft description which will be analyzed and further mapped into different platforms. Refined code is migrated to four different processor architectures: a processor research framework (CRISP-Trimaran), a soft core processor with specific functional units implemented on an Altera FPGA, an ASIC and a classic DSP.

In this paper we describe the implementation in SystemC of a scalable and parametrical network on chip (NoC). The NoC, with a mesh topology and wormhole routing, is formed of resources and routers connected by channels. Each router is connected to four neighbours' routers through input and output channels. The channels of the routers have a data bus and two control signals to let a communication based on handshake. A wrapper establishes the communication between the resource and its environment converting the messages into a format appropriated for the NoC. The information is packed to be able to circulate through the NoC and it is unpacked when it arrives to the destination

Future multiprocessor system-on-a-chip (MPSoC) will need high performance and low power requirements due to user demand and limited battery life. In this paper, we take advantage of the architecture flexibility allowed by Network-on-Chip (NoC) to build a parameterizable MPEG Compressor. MPEG compressor System has been developed in synthetizable behavioural SystemC, as a flexible system divided in different tiles. Each tile can be configured as a functional block with different performance parameters in terms of power/speed/area. NoC design implements a 2D mesh with a parameterizable router implemented in high level TLM SystemC. A QoS module takes decisions on packet routing depending on macro-block encoded data (corresponding to I, P and B frames) in real time in terms of power or performance requirements.

Time needed to set-up and send new products to the market is a crucial factor for success, so one important rule is to develop your product as quickly as you can. In the electronics world the systems normally contain some parts in HW and others in SW being the HW/SW partition a crucial issue in the cost-performance trade-off. A bad choice usually requires the redesign or remaps of some parts the system with the consequent waste of time and money. In the last years many new concepts appeared for the design of systems, with the called HW/SW co-design based on system (SoC) and virtual components. Those concepts rely to methodologies that try to integrate HW and SW design techniques in just one consistent system-level methodology allowing to work in a way that is more secure (specifications and developments are verifiable), more efficient (cost analysable) and that can be automated (through systems synthesis). Demonstrator based MPEG video compression has been designed and validated. It implements video coding using the standard ISO/IEC 13818-2 I ITU-T H.262H (also know as "MPEG2 Video"), for the main profile at main level (720/spl times/480, 30 fps). The encoder implements frames I or I-pictures.

In complex reconfigurable systems on chip, the dynamism of targeted applications requires an efficient management of platforms. To enable run-time resource management, operating system and reconfigurable SoC platform should be developed together. In this context, additionally to the issues inherent to hardware and software design development, we have to deal with the supplementary difficulty of the interaction between software and hardware, and of both with the platform. In this paper we present a real-time debugging tool operating in a mixed hardware and software environment. This dynamically loadable tool seriously decreases the time required for debugging while the overhead in terms of additional code is minimal.

Abstrac(- This paper shows the design of the IFFT module corresponding to the baseband processing of an OFDM transmitter according to the IEEE802.11a-g and Hiperlan/2 standard. This module will be included in a future OFDM demonstrator, which will be implemented into a progranunable logic device. We have used our own algorithm for IFFT computing. It is based on the recursive properties called decimation. This algorithm offers optimal characteristics for the hardware implementation: a high degree of parallelism and exactly the same interconnection pattern between any of the algorithm stages. A new point of view in the prototyping design flow and the verification process comes from the use of the last generation system level design environments for nsP" into FPGAs. These environments, called visual data flows, are ideally suited for modeling DSP systems sinc:e they allow a high level of functional abstraction with different data types and operators.

This paper describes the configurable computing paradigm and discusses its application to real-time industrial visual inspection applications. Automated visual inspection (AVI) applications are briefly described, discussing their requirements over electronic and computing systems. Different technological alternatives usable in these systems are compared. The implementation of a complete configurable computing system is described discussing the different choices in every design step. The system is based on the PCI bus and uses a personal computer as host, with Windows95-98 operating systems. This host computer is in charge of controlling and configuring the designed hardware to map the requirements of AVI applications. The system described is structured using a modular approach that allows users to customize their system to fit the resources required by their applications.

The construction of a system that recognizes vehicle license numbers using feedforward neural networks, after the numbers have been extracted using classical methods, is described. The system is trained and tested on real-world data. In order to reduce the total amount of memory required and increase the process speed, an additional step is added to the learning algorithm that produces low precision weights (+1, 0, -1). The network obtained after this training process has a behavior similar to those networks using floating point representation for weights. A special hardware accelerator is developed to achieve high-speed recognition. >

This paper introduces a new PCI-based system targeted to prototyping implementations of image processing (IP) in computer vision applications with reconfigurable devices. The system is composed of an image digitizing board and a reconfigurable coprocessor with a new architecture for local memory. The paper describes the implementation of these two boards and discusses the design of a new functional programming environment. This environment is based on a library of parameterized modules implementing some of the most common operations in image processing. Two examples of these modules are overviewed and a new architecture for image convolution is presented.