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This paper presents a microwave implementation of the novel sequentially-switched delay line (SSDL) for simultaneous transmit and receive (STAR) applications. The circuit is nonreciprocal and non-magnetic and is implemented in a high frequency GaN MMIC process. It isolates the transmit and receive paths. Measurements confirm the non-reciprocal nature of the circuit. The insertion loss is 5 – 8 dB with 20 – 35 dB isolation over DC-2 GHz.

A fast interval-halving search is demonstrated that can be used to optimize power-amplifier load impedance in real-time with a high-power evanescent-mode cavity tuner, consisting of two evanescent-mode resonant cavities. The power-added efficiency is optimized by tuning the resonator position numbers, which map to resonant frequencies, without need for a load-pull characterization. Because no characterization is required, significant time savings in computation is expected, and tuning is expected to be more robust to drift and hysteresis of the tuner characteristics.

The rapid progress towards 5G wireless systems is accelerating the development of mm-wave semiconductor processes, broadband circuits, and system technologies. Similarly, next-generation radar is being expanded and redefined. Legacy radar systems are nearing the end of their life cycle and systems developers are aiming to upgrade their capability while reducing cost, size, and weight. Radar systems have requirements that result in technical circuit design challenges including high power, broadband, and low distortion. This paper focuses on MMIC design challenges specific to the design of next-generation radars that will operate in a crowded wireless environment, allow spectrum sharing, and dynamic frequency selection. Simulated and measured data are presented.

For future adaptive radio and radar transmission in a dynamic spectrum access environment, the radio-frequency circuitry will be need to be reconfigurable to allow adjustment of the operating frequency and the transmission spectrum in a congested environment. A prototype tunable amplifier matching network was implemented using varactors as the tunable elements. A method in which the control bias voltages of the varactors are directly tuned is compared with a previously demonstrated algorithm that tunes based on the reflection coefficient through a nonlinear characterization of the varactor matching network. The algorithms are both designed to optimize the power-added efficiency of the amplifier while keeping the adjacent-channel power ratio below a pre-specified constraint value. Lower average time per measurement is achieved for the voltage-based search, but the total search time is lower for the reflection-coefficient based search. This comparison of algorithms is useful in developing a reconfigurable transmitter amplifier that can adapt on the fly to meet changing spectral requirements.

Fast load impedance tuning of a varactor diode matching network to maximize amplifier gain in real-time reconfigurable circuitry is demonstrated. A published tunable varactor-diode matching topology is designed for operation at 1.3 GHz to provide significant Smith Chart coverage. A steepest-ascent algorithm is applied for fast optimization, and measurement results indicate excellent convergence from multiple starting points within the Smith Chart. Algorithm data compares well with traditional loadpull results measured with both a commercially available tuner and the tunable-varactor network, and searching with the varactor tuner search is much faster than a traditional mechanical tuner.

The MMlC designer has several options available to verify the performance and simulation agreement of his circuits. They can be divided into two basic categories: calibration reference plane at the probe tips or on the MMIC chip at the coplanar interface to the device under test (DUT). The calibration technique used determines the reference plane of the measurements. Several on-wafei and off-wafer calibration techniques were used to obtain measurements of GaAs MMICs. A Wafer Probe station and a vector network analyzer were used to obtain LRM, SOLT, and TRL calibrated measurements of GaAs devices. In order to use on wafer calibration, an open, a short, a load, a "short" microstrip line, and a "long" microstrip line were designed and included on the GaAs wafer. An SOLT and a TRL calibration was performed with these on-wafer calibration standards. For off-wafer calibration, the Cascade Microtech Impedance Standard Substrate (ISS) was used to obtain an LRM calibration for a third set of measurements. To equalize the reference plane of the LRM measurements with the on-wafer TRL and SOLT calibration measurements, the MMlC launches which transition from the coplanar probe to the microstrip were subtracted out, i.e. deembeded to equalize the reference plane. A numerical technique was used to extract the approximate s-parameters of the MMIC launch from LRM measured data. Device measurements with all three calibration techniques closely agreed and were repeatable. These deembeded measurements compared favorably to foundry supplied device models.