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This paper presents an all CMOS decibel-linear Automatic Gain Control (AGC). This AGC achieves large dynamic range with low power consumption. By applying digital switches to change exponential approximation function, four dynamic ranges (62, 50, 33, 26 dB) are realized. This AGC is implemented in TSMC 0.18-µm CMOS RF process. Measurement results show that this AGC achieves 60 dB linear range with linearity error less than 1 dB. The whole circuit consumes 3.6 mA from 2-V supply.

With supplied by the battery, the low power consumption of OBU system chip in ETCS is demanded. This paper designs a low power wake-up circuits applied to OBU system chip. The circuit system extracts envelope signal from an amplitude shift keying (ASK) modulated 5.8 GHz carrier and converts it to digital signal. Only the envelop signal that the frequency of it is 14 KHz can produce the wake-up pulse, which effectively prevents error wake-up caused by other frequency signals. By incorporating an input impedance matching network, the wake-up circuits achieve input sensitivity of −35 dBm and the S 11 of the match network is −19 dB with 50 Ω input impedance. Measurement results show the dc current is 6 uA from 2.4 V to 5 V supply. The wake-up circuits is fabricated in TSMC 0.18 μm RF CMOS 1P6M process and the entire chip occupies an areas of 375×330 μm2.

This paper presents a 5.8 GHz low noise amplifier (LNA) for electronic toll collection system (ETCS). Traditional design strategy of source inductor feedback amplifier (L-CSLNA) ignores the influence of off chip matching, such as print circuit broad (PCB), bonding wire and passive chip parts which greatly affect the performance of LNA at high frequency. In this paper we adopt 3D electromagnetic simulation to analyze the impacts of off chip components to the design of LNA. The proposed LNA has been fabricated in 0.18 μm CMOS process. The measured S11 of the proposed LNA is less than −10 dBm from 5.7 to 5.9 GHz, the minimal noise figure (NF) is 2 dB, the maximal power gain is 12.7 dB and the IIP3 is −4 dBm with 16 mW power dissipation.

This paper introduces a CMOS operational amplifier with constant transconductance, suitable for operation in low voltage environments. A constant transconductance is ensured for the whole common mode input stage which is based on flipped differential pairs. The proposed operational amplifier is designed to operate with a 1-V supply and is implemented in 0.18-μm standard CMOS technology. The results show that a closed-loop unity-gain bandwidth achieves 7.6 MHz and an open-loop low-frequency gain is higher than 73 dB with a 1-MΩ‖15-pF load.