Search

This article presents a novel space vector pulsewidth modulation (SVPWM) for a three-phase binary-cascaded multilevel inverter (BCMLI). The SVPWM could become impractical in multilevel inverters (MLIs) because of its increasing complexity with a larger number of levels. The gh coordinate system can ease the digital implementation, but to generate the inverter's abc states from the nearest three vectors (NTVs), iterative computations are required every sampling instant. This article proposes a further reduction of computations by directly generating the abc state with minimum common-mode voltage (CMV) from a gh vector. Subsequently, only one vector among the NTVs is required for implementing the proposed SVPWM. The reduced CMV profile within the NTVs further permits the reduction of commutations by clamping one phase during a sampling period. The presented technique exhibits full dc bus utilization capability and can be implemented in the BCMLI and further applied to any M-level MLI. Also, if M is considerably large or if switching losses and electromagnetic interference emissions must be minimized, nearest vector modulation with reduced CMV along with the line-frequency operation of high-voltage cells can be implemented to reduce the switching losses. Experimental results of a BCMLI are presented to verify the effectiveness of the proposed technique. Published version

The inverter that requires isolation typically consists of an isolated dc-dc and a pulse-width-modulated dc-ac stages. However, the component counts, control complexity, efficiency and power density tend to be suffered with such a two-stage configuration. In this paper, a single-stage soft-switching isolated inverter based on MHz LLC converter is introduced with a novel hybrid modulation method, which operates under full-bridge and half-bridge variable frequency conditions for high- and low-line outputs, respectively. A rectified sine wave can be generated at the output of LLC converter and isolated through a high-frequency transformer for additional voltage gains. A lossless line frequency unfolder circuit is added afterwards to convert the rectified sine wave to ac sine output. The optimization method for the resonant tank is also proposed to achieve even lower voltage gains at high frequency to improve the output ac waveform quality. Compared to the traditional two-stage method, this single-stage solution makes the circuit simpler, and the bulky dc bus capacitor can be saved. To verify the circuit design and the proposed hybrid modulation method, a GaN based 380 V dc – 600 V ac , 1.2 kW prototype is built and tested. Under the full load condition, the measured total harmonic distortion of output voltage is 2.67% with 98.30% efficiency for the overall inverter.

This paper introduces a hybrid binary cascaded multilevel inverter (BCMLI) that allows the supply voltage of the lowest level to be a floating capacitor and thus reducing the need of multiple separated sources. Multiple such BCMLIs can be cascaded to increase the number of levels. This paper extends the configuration with two of 3-cell hybrid BCMLI modules cascading to achieve 29 voltage levels. A utility-scale hybrid BCMLI was designed and built using a single-source as the input and LLC converters to produce the 2-kV, 11.2-kW step-like output with 15 voltage levels. Two of such units were further cascaded to produce the 4-kV, 22.4-kW step-like output with 29 voltage levels. The circuit and control have been designed and simulated, and the hardware prototype has been built and tested. The total harmonic distortion was measured at 3.5% under the full-load condition. The LLC stage is a gallium nitride based converter operating at 1 MHz for an ultra-compact design. As the only loss is on the LLC stage, and high-voltage side is nearly lossless, the overall system efficiency exceeds 98.8%.

LLC resonant converter is widely used for isolated dc-dc power conversion applications due to its soft switching characteristics and simple structure. With the help of wide bandgap (WBG) devices, the switching frequency can be pushed to MHz range and the transformer loss becomes a more critical factor for the efficiency of the whole LLC converter. The high frequency effects, such as skin effect, proximity effect and fringing effect, make the transformer design even more challenging. Many research have been performed to evaluate core loss and copper loss from calculation, simulation or direct measurement in specific tester circuits. However, they are different from real circuit conditions. In this paper, the design principles and optimization considerations for the transformer in MHz LLC converter are presented. An accurate test-based method for core loss and copper loss estimation is proposed. Based on the proposed method, several optimization considerations are provided. To verify the optimized transformer design and its loss prediction method, a GaN based 1 MHz/2.8 kW LLC converter prototype is built, which can achieve 99.04% peak efficiency.

LLC resonant converter is popular for dc-dc converter designs due to its simple topology, galvanic isolation and soft switching capability. Therefore, lots of researches have been performed for LLC converter design and optimization to pursue high efficiency and high power density with high switching frequency. However, relevant research about the analysis and ZVS model for LLC converter with light load condition under MHz switching is scarce. In this paper, detailed analysis for MHz GaN based LLC converter is provided with light load. Moreover, a simple and accurate ZVS model is proposed, which can help determine fully ZVS condition for primary side devices. To verify the analysis and the proposed ZVS model, a 1 MHz/300 W (10% load) GaN based LLC converter prototype is built and tested.

For wide gain range applications with LLC resonant converter, variable frequency modulation is widely used to achieve different output voltage. The first harmonics approximation (FHA) is one of the most popular adopted methods to calculate voltage gain with different switching frequency. However, it is not accurate when the switching frequency is far away from the resonant frequency and the diode effect on voltage gain makes FHA deviate from the actual results even more. Several models have been proposed to solve the drawback of FHA method that only first harmonic of the resonant current is examined. Few of them takes the diode effect on voltage gain into consideration. In this paper, detailed analysis of diode effect on voltage gain is presented and based on the analysis, an accurate voltage gain model for LLC converter is proposed. To verify the proposed model, a 1.6 kW GaN based LLC converter prototype is built and tested at 700 kHz and 1 MHz.

Since the last decade day by day, there is a revolution in an existing power grid network due to an increase in demand for the convenient electric power supply required for the smart component in the power grid network. So this is a time for the power grid to become smart in accordance with all components which are actively participated in his network which is nothing but Smart Grid network. A different component in a Smart grid network required variable AC/DC power supply at the different amplitudes and different frequencies. Power electronics converters are required to meet all these requirements. Solid State Transformer (SST) is one of the key components in a smart grid network. This paper presents the Bidirectional Soft Switched Solid-State Transformer for a Smart Grid Network. A proposed circuit presents in this paper used a LCLC type resonant network to achieved soft switching action. An analysis of the resonant network and it's effect on the performance indices are presents in this paper. A front end bidirectional boost rectifier is used in a proposed circuit to achieved bidirectional power flow feature and desired voltage gain at the output. A proposed circuit is designed for power level 10KW and is simulated in a PSIM/Simulink co-environment. The results were obtained at an input voltage of Three-phase 440V, 50 Hz, and provide the output of 800V, 12.5A and is verified for desired features in the proposed converter.

In unidirectional LLC converters, synchronous rectification (SR) is a technique that can be implemented to minimize the conduction loss of the secondary-side LLC rectifier. In drain-source voltage-sensed SR, a premature turn off issue can be observed due to parasitics present in the drain-source voltage sensing loop. In this digest, a novel use of multilevel gate drivers (MLGDs) and digitally adaptive control for multilevel turn-off can be implemented to mitigate parasitic effects, boost efficiency and the applicable load range of drain-source SR. Multilevel gate driving boosts the sensed SR signal strength, extending the total SR conduction period. This driver can be combined with an adaptive delay block to maximize efficiency. Because the increased drain-source signal integrity is increased at the turn-off moment, this also prevents an oscillation issue at light loads. Overall rectifier efficiency is increased over a traditional gate driver or non-adaptive MLGD due to a reduction in parallel diode conduction from tuning the transition point. The concept of the adaptive multilevel gate driver is proposed, explained, and simulated in this paper. A discrete multilevel gate driver is built and an adaptive delay block designed in a FPGA and tested on a LLC-DCX resonant converter for proof of concept.

This paper focuses on the LLC resonant converter working in the zero-voltage-switching (ZVS) region where the switching frequency (f s ) is larger than the resonant frequency (f r ). The secondary side devices critically affect both the normal operation and deadtime operation of the LLC converter. The effect of diode junction capacitance (C j ) and reverse recovery on the ZVS condition during deadtime has been discussed in the literature, but their effect on the waveform during normal operation has not. In this paper, a detailed description and analysis of deadtime operation with Silicon and Silicon Carbide (SiC) diodes are provided firstly and an accurate model for their effect on the following normal operation is derived based on the deadtime analysis. From the derived model, an improved ZVS condition for f s > f r region is presented, which can also provide the guideline for the selection of secondary side devices. To verify the proposed analysis and model, a 694 kHz/100 W GaN based LLC converter prototype with different secondary side devices is built and tested.

This paper presents implementation of triangular critical conduction mode (CRM) modulation scheme to three-level boost (TLB) converter and proposes a three-level CRM modulation scheme for the topology. Compared to conventional triangular method, the proposed one performs full-utilization of three-level capability and synthesizes quadrangular inductor current waveform. By adjusting a designable period of the proposed scheme in a switching cycle, several variables including operating frequency, inductor current peak and component rms currents can be decreased. As a result, converter efficiency can be improved and current stresses of circuit components can be mitigated. In this paper, details of TLB operation principle, analysis of the proposed scheme and effects of adjustable design parameter are provided. A 700-W TLB converter prototype has been set up in order to verify the effectiveness of proposed CRM modulation scheme.

Gallium Nitride (GaN) devices have shown greater potential in high switching frequency operation due to its much lower switching loss compared to Silicon devices. However, the faster switching speed makes it more difficult for device dynamic characterization because it is more sensitive to the parasitic components in the circuit and it requires better testing equipment. Double Pulse Test (DPT) is commonly used to characterize device dynamic performance and proper device drain current probing method is a must for accurate switching loss measurement. However, for GaN devices designed to have loop inductance within sub-nH range, any coaxial shunt to measure drain current will insert enough parasitic inductance to influence switching performance and impact measurement results. In this paper, a novel and simple method is proposed to accurately evaluate switching loss without shunt resistor in series with GaN device in a half bridge configuration, which is a common building block in power electronics circuits. A 130 W GaN based buck converter prototype is built to verify the proposed method.

The series resonant dc-dc converters are mature technology used mostly in applications requiring constant dc voltage gain. They were recently enhanced by the application of the boost rectifiers. This approach showed new opportunities for input voltage regulation range extension. The given paper summarizes known operating modes and shows a way of significant input voltage range extension through the utilization of hybrid full-bridge switching cell. Two converter topologies are introduced in this paper. Possible operating modes are identified and summarized.

High frequency PCB windings magnetic is one of the key components in high power density and high efficiency MHz power converter. High frequency PCB windings magnetic losses are the main limitation for the whole converter efficiency and power density, while the PCB windings losses are the main part of the magnetic losses. Currently, the Dowell’s model is used for the layout of PCB windings. However, the Dowell’s model has its restrictions, namely, magnetic field is assumed to be distributed evenly in one direction. But the magnetic field around the windings are three-dimensional and unevenly. Therefore, further arrangement of PCB windings is proposed to minimize the PCB windings losses. Besides, the magnetic circuit is analogous to electrical circuit, and the magnetic core structure shape the footprint of the PCB winding, so different magnetic core structure can be proposed for the trade-off design among the high power density, high efficiency, and low temperature stress. Therefore, both PCB winding layout and magnetic core structure design are important for the optimization of high frequency magnetic components.

LLC resonant converter is widely used due to its high efficiency and high power density capability. The design methodology for it has been addressed in many literatures. However, most of them focus on the step-down LLC converter due to its high-output current applications such as data center. In this paper, the optimal design methodology for high frequency GaN based step-up LLC converter for solid-state transformer application is discussed. An accurate model for deadtime operation is derived. From the model, the approach for device selection for both primary and secondary sides and the magnetizing inductance design to have zero-voltage-switching (ZVS) are presented. To verify the design methodology, LTSPICE simulation is performed. Besides, a 1 MHz 1.8 kW step-up LLC converter prototype is designed and tested. With the proposed design methods, the efficiency can achieve 98.75%.

Due to high efficiency and simple structure, LLC resonant converter is a promising topology for developing solid-state transformers. The heart of an LLC converter is the high frequency transformer that provides necessary insulation and step-up/down between primary and secondary sides. In addition, the efficiency of the transformer is a critical factor as it processes the entire power. This becomes even more challenging when circuit switching frequency is raised for shrinking passive component sizes, as skin effect and other non-ideal effects start to kick in. In solid-state transformer applications, size, efficiency and insulation have stringent specifications and meeting all requirements at once is not a simple task. Therefore, this paper presents multiple perspectives in terms of transformer design in an LLC converter and demonstrates with a 3-kW transformer capable of more than 15 kV insulation. Testing results show peak converter efficiency of 98.9% with transformer power density of 480 W/in3.

A novel auxiliary resonant snubber is introduced. The design and operation are carried out, in which this snubber circuitry enables main Gallium Nitride (GaN) switches operating under zero voltage switching (ZVS) condition, and auxiliary Silicon Carbide (SiC) diodes switching under zero current switching (ZCS) condition. Besides, the auxiliary snubber circuitry gating algorithm is also optimized which allows reducing the switching and conduction loss in auxiliary GaN switches to obtain higher system efficiency and better thermal performance. This proposed inverter can be applied to wide range of potential applications, such as string solar inverter, renewable energy combined distributed generation, dc-ac part of bi-directional electrical vehicle (EV) on-board charger, and uninterruptible power supply (UPS), etc.

A front-end for multi-generator power system was recently proposed, which utilizes a single wye-delta (Y-Δ) transformer to shunt between the two 30° phase-shifted generator outputs. The shunt type phase-shift transformer front-end provides comparable 5th and 7th harmonic elimination performance to the conventional 12-pulse rectifier with more than 75% transformer size reduction. In this paper, a hybrid front end, which consists of the shunt Y-Δ transformer and an active power filter is proposed to further improve the power quality. In this configuration, 11th and 13th harmonics from nonlinear load are actively compensated by the active power filter and 5th and 7th harmonics are trapped by Y-Δ transformer. Theoretically, the performance of the proposed front end is equivalent to a traditional 24-pulse rectifier with a significant reduction in the overall size and weight, which makes it attractive to large-scale industrial and shipboard applications. The harmonic cancellation principle of the proposed front end is derived and verified by simulation and experimental results.

Drain-source voltage-sensed synchronous rectification (SR) is a technique used that can be used to reduce the secondaryside diode conduction loss of an LLC converter. In drain-source SR, an early SR-switch turn off issue is observed due to parasitics present in the power path of the rectifier drain-source sensing loop. In rectifiers with parallel switches, sequential parallel switching (SPS) can be utilized to increase the drain-source signal integrity near turn off. In rectifiers where a single SR switch is used, multilevel turn-off can be used to reduce the parasitic effects and allow for a more accurate SR turn-off. By reducing the gate voltage prior to SR turn-off, the drain-source voltage signal near the turn-off moment can be boosted to minimize the parasitic drain-source phase shift effect, extending the total SR conduction time. Multi-level turn off also reduces the amount of turn-off edge jitter experienced, which can start an internal unstable resonance at light-load conditions. By increasing the SR conduction time, multilevel turn-off can decrease body or antiparallel diode conduction loss in the LLC rectifier. This results in a net increase in total converter efficiency, despite a small increase in the SR FET channel conduction loss from the prolonged channel conduction time. A discrete three-level multilevel gate driver is built to test this concept, simulations are in the process of being run, and verification with silicon carbide SR FETs is performed on a 2.5kW LLC-DCX module.

This paper presents small-signal modeling of three-level boost (TLB) converter for active front-end power-factor-correction in medium-voltage (MV) solid state transformer (SST). The analysis has been conducted for continuous conduction mode (CCM) in two different voltage modes of TLB to derive system dynamics and to confirm that transfer functions in the voltage modes are identical to one another. Based on the derived models, this paper introduces MV-SST system design guidelines including controller and input filter, considering limited selection width of off-the-shelf high-voltage-rating capacitors and nontrivial source impedances. Digital feedback controller and input filters are designed based on the derivations and implemented to a 4-module-stacked SST system prototype of which TLB plays a role of active front-end PFC. In order to verify the effectiveness of small-signal analysis and system design, experimental verifications of the prototype have been conducted for single phase 3.8-kV rms input voltage to 400-V de bus voltage conversion and 15-kW full load condition in the existence of 65-mH source impedance.

This paper proposes a hybrid-mode Cuk inverter with low-voltage ride-through (LVRT) capability under grid-faults. It operates as an unfolding-type inverter during normal grid condition and two-stage inverter during abnormal grid condition. Thus, it normally transfers the energy to the utility grid highly efficiently, and also has the LVRT ability under grid-faults. Moreover, two types of inverters share the full-bridge circuit on the grid-side and so the proposed circuit can be developed with low cost and reduced size. This paper outlines operation principles and control methods for the proposed inverter. The prototype of the proposed converter was implemented and experimental tests were carried out to demonstrate its practical feasibility.

Switched reluctance motor (SRM) has double saliency structure and operates under the saturated condition to achieve high energy conversion ratio. Therefore, the magnetic characteristics of switched reluctance motor is highly non-linear that the actual inductance profile can not be simply obtained by the inductance measurement instrument. As the control performance of SRM drive is highly dependent on a priori knowledge of magnetic characteristics, the accurate measurement is important. This paper presents the incremental inductance measurement method through closed loop current control. The rate of change of the phase current is captured by additional sampling instant. The effects of phase resistance variation, core loss, and power device voltage drop are considered to minimize the measurement error. The measurement results are verified with LCR meter and torque transducer measurement.

Tapped-inductor (TI) buck converter is capable of high step-down conversion with extended duty cycle over traditional buck converter. Additionally, its synchronous conduction mode (SCM) can completely eliminate turn-on losses, allowing high switching frequency operation and subsequent high power density. Nevertheless, the converter efficiency under SCM is refrained by circulating current and therefore a dual-loop (DL) control is proposed in this paper. Based on a time-domain model for zero-voltage-switching (ZVS) process, the DL control has a variable-frequency (VF) outer loop to minimize both ripple-current conduction loss and dead-time loss. While the VF loop moderately adjusts switching frequency, an inner voltage-mode-control (VMC) loop regulates output voltage. To verify the idea, a MHz-level, 15-W, DL-controlled TI buck prototype is built. Experimental results demonstrate the efficiency-boosting effect of the VF loop especially under light load. Finally, the derived plant model of TI buck converter under VMC is introduced in the paper along with the feedback design for output regulation.

Drain-source synchronous rectification (SR) is a technique used to reduce the secondary-side conduction loss of an LLC resonant converter. In drain-source sensed SR, an early turn off issue can be observed due to parasitics in the drain-source voltage sensing loop. In LLC converter rectifiers where multiple SR switches are paralleled, sequential parallel switching (SPS) can be implemented to sequentially turn off the SR FETs to reduce the effect of these parasitics. By turning off SR FETs one by one over batch turn-off, the drain-source voltage signal near the turn-off moment can be enhanced, mitigating the effects of parasitics and the subsequent early turn-off issue. This method also reduces the amount of turn-off jitter experienced with low on-resistance (R DS,on ) FETs, which can start a detrimental resonance at light load conditions. Since the SR conduction time is prolonged, SPS can decrease body-diode/anti-parallel-diode conduction loss in the rectifier. This results in a net increase in converter efficiency, despite a slight increase in the SR FET’s channel conduction loss. The concept and operation of SPS is proposed, explained, and simulated in this paper. Finally, SPS is implemented and verified at light load on a LLC resonant converter with paralleled GaN SR FETs.

The LLC series resonant converter is widely used in many applications due to its high power density and efficiency. However, under applications with relatively small magnetizing current and resonant inductance such as DC transformer (DCX) for telecom power systems and PV optimizers, the resonance between the leakage inductance and the secondary parasitic capacitance during dead-time is unneglectable. It will affect the zero-voltage switching (ZVS) transition and the resonant current during the power delivery period. Therefore, in this paper, two different scenarios of the ZVS condition for an LLC series resonant converter with secondary parasitic capacitance considered will be presented. Moreover, the impact of the resonant to steady state operation under different ZVS timing will be discussed. Experimental results of a 140kHz prototype are provided for verification.

This paper analyzes CCM/DCM operations of three-level boost (TLB) converter and derives ideal duty-ratios for feedforward control in power factor correction (PFC) applications. The analyses are conducted for two different TLB operation modes characterized by input voltage range. Since duty-ratio feedforward is a widely used technique to improve PFC transient responses and mitigate the burden of feedback control, accurate duty-ratio computations for all possible operation modes and conduction modes are necessary. By comparing the derived duty-ratios for CCM and DCM regions, current conduction modes of TLB can be detected in real-time and proper duty-ratio feedforward with minimum duty-ratio selection can be provided. The experimental results by a 500 W prototype of TLB PFC rectifier are provided in order to verify the effectiveness of the derivations and feedforward technique.

This paper proposes a memory space adjustable repetitive controller (RC) for an unfolding-type isolated Cuk inverter operating in the continuous conduction mode (CCM). To achieve acceptable tracking performance with reduced computation burden and memory space, we use the memory space adjustable RC in addition to the proportional-integral (PI) controller and the feedforward controller. Two right-half plane (RHP) zeros in the transfer function of the Cuk CCM inverter cause phase lag of the closed-loop control system. To compensate for the phase lag accurately under the low-sampled environment, we develop a fractional-order phase-lead compensator in the memory space adjustable RC. Simulation and experimental tests using a 300-W unfolding-type Cuk CCM inverter have verified the proposed controller achieves desirable performance.

Nowadays, high power density is one of main pursuits for power converters. High switching frequency can greatly reduce the size of passive components. With the availability of wide bandgap devices, the converters have opportunities to operate at megahertz switching frequency with higher efficiency and power density. However, unlike the conventional kilohertz switching, parasitic inductances induced from the printed circuit board (PCB) could significantly affect the circuit operation under megahertz switching. In particularly, the parasitic effects will be enlarged for high step-up or step-down isolated converters, since the parasitic inductances are square times the turns ratio of the transformer when reflecting from low voltage side to high voltage side. This paper takes LLC converter as an example to discuss the optimization of PCB layout to reduce the parasitic effects with finite element method. In the experiments, a couple of 1-MHz 38V/380V 300-W LLC resonant converters are built and compared to verify the design optimization.

A high step-up constant frequency resonant converter with PWM controlled active boost quadrupler rectifier (ABQR) is proposed in this paper. The proposed converter operates at the resonant frequency throughout the whole operation region to achieve the highest efficiency. Under low input voltage conditions, the quadrupler based active boost rectifier will operate with the proposed PWM modulation scheme to step up the voltage. With the proposed ABQR, the output switches serve both for synchronous rectification and voltage boost function. It enables a higher voltage boost ratio than series resonant converter. Moreover, the voltage stress on secondary power devices are reduced to half of the high output voltage and the transformer turns ratio can be lower. A 300-W hardware prototype with gallium-nitride devices is built to verify the performance of the proposed converter and modulation method. It can achieve a peak efficiency of 98.9% and a California Energy Commission weighted efficiency of 98.7% under nominal input voltage condition.

In this paper, the low voltage stress of switches, high voltage gain DC-DC converter is proposed. The operating principle of the converter is similar to that of the conventional buck converter. Therefore, the proposed converter can be operated in the discontinuous conduction mode, continuous conduction mode, depending on the design. Moreover, the controller is also similar to that of the traditional buck converter, results in the simple controller. Furthermore, the voltage stress of every switch is reduced significantly compared with the conventional converter. Therefore, the use of the low voltage rating switches reduces the losses significantly. A 200W converter prototype is successfully built and tested to verify the feasibility of the proposed converter.

A 12-pulse rectifier has been widely used for harmonic mitigation in a large-scale power system. Recently, a shunt phase-shift transformer rectifier was proposed and already has been utilized in a marine transportation. For a power system equipped with multiple generators, the shunt phase-shift transformer front-end selectively eliminates 5th and 7th harmonic component with more than 75% size reduction over the conventional 12-pulse rectifier. However, a shunt phase-shift transformer rectifier requires additional source inductors to eliminate the undesired harmonics and the relationship between the source impedance and harmonic elimination has not been verified. This paper evaluates the effect of the line inductor on a harmonic cancellation performance of the shunt phase-shift transformer. An equivalent circuit analysis and a mathematical derivation of the shunt phase-shift transformer rectifier are provided and the relationship between the source impedance and harmonic cancellation is mathematically derived. The computer simulation and experimental test results from proto type hardware verify the equivalent model and the mathematical analysis.

In this paper, one single leg T-type converter with full silicon carbide (SiC) half-bridge power modules and hybrid power modules combined silicon carbide (SiC) with silicon (Si) power module, are designed and investigated. Firstly, the switching characteristics of Cree SiC device CAS300M12BM2 and Semikron SiC device SKM350MB120SCH17 single-leg T-Type converters are compared with double pulse testing (DPT). Then, to further investigate the performance, the hybrid power modules of the single leg T-type converter with Cree SiC device CAS300M12BM2 and Semikron Si device SKM300GM12T4 are built, which can increases the power density, compared to the full SiC devices T-type converter. To suppress the ringing of the middle leg switching device, the resistor-capacitor (RC) snubber are designed and demonstrated with DPT. Finally, the function testing of the hybrid single leg T-type converter are experimentally verified. Nanyang Technological University National Research Foundation (NRF) Accepted version This research work was conducted in the Rolls-Royce@NTU Corporate Lab with funding support from the National Research Foundation (NRF), Rolls-Royce and Nanyang Technological University; under the Corp Lab@University Scheme.

Increasing usage of high output voltage, low output current resonant-based DC-DC converter systems can face a stability issue when cycle-by-cycle drain-source synchronous rectification (SR) controllers are paired with low RDS, on rectifier switches. A current resonance phenomenon can be observed at low power conditions within the LLC resonant converter. This instability can lead to inconsistent SR operation, excessive conduction loss, output ripple, and poor light-load efficiency. In this paper, the issue is root caused, simulated, and an FPGAbased duty cycle rate limiter is built and tested to verify a possible method of alleviating the issue.

This paper investigates the effects of low frequency harmonics and source impedance on active front-end rectifier in modular solid-state transformer. The topology for analysis was selected to three-level boost (TLB) converter which is widely used for power factor correction. Harmonic contents of input source cause periodic distortions in input current, degrading THD factor. In the presence of finite source impedance, performance of properly designed current controller can be deteriorated in terms of phase margin and system instability. In this paper, those external effects are studied with equivalent single module TLB. Repetitive controller and input filter designs are presented to compensate periodic distortion and overlapped impedance interaction in frequency domain, respectively. Simulation and experimental results are provided to verify the analysis.

High switching frequency (HF) operation of solid-state transformers (SSTs) reduces the weight and volume of magnetic parts. Yet in medium-voltage (MV) SSTs, electrical insulation becomes a great concern and demands extra spacing. To resolve the issue, resistive shielding technique is considered in this paper to mitigate the threat of partial discharge. In addition, geometric shaping is applied to alleviate local electrical field. On top of the insulation and size requirements, HF transformer design should also consider skin effect and other effects induced by ac electromagnetic field. This paper is meant to develop a planar transformer for a MV SST, taking all critical factors into account. 2-d finite element analysis is adopted as main research and conceptual verification method.

A position sensorless control method for switched reluctance motors from standstill to running without pre-stored magnetic characteristics is proposed. For startup, diagnosing pulses are injected into all three phases, and the current magnitudes of all phases are examined to estimate the rotor position. Additionally, a phase current vector method is applied to eliminate the risk of locked-rotor and startup hesitations. In running condition, diagnosing pulses are injected to two non-torque productive phases to estimate the position and commutation instant. An angle tracking observer estimates the continuous angle from the acquired discrete position information. The proposed method does not require any prior knowledge of the switched reluctance motor except the pole configuration. Therefore, memory storage for magnetization curves of a switched reluctance motor is not needed. The experimental results show a hesitation-free startup, a good speed reference tracking, and an accurate position estimation performance under different load conditions.

In this paper, a high-efficiency solar optimizer with a new modulation method is proposed for wide range regulation. The converter is designed as a series resonant converter under nominal-input condition where the voltage step-up ratio is entirely determined by transformer. A new modulation method with fixed switching frequency is proposed to gain a higher voltage step-up ratio for low-input conditions. The proposed modulation method does not add any auxiliary power switches compared with previous works while it yields wide range regulation. A 300-W hardware prototype using Gallium-Nitride devices is built to verify the performance of the proposed solar optimizer.

Non-isolated step-down converters are widely used as auxiliary power supplies. Active and passive components, excluding large magnetic components, are usually integrated in a single chip in the industry. High power density and high efficiency are always the most important requirements. High switching frequency, such as megahertz (MHz), can highly shrink the volume of passive components compared with kilohertz frequency, however, it will cause huge switching loss for hard switching converters. Zero-voltage-switching (ZVS) is able to highly reduce switching loss, especially under high switching frequency. In this paper, three ZVS buck-type converters operating at MHz frequency, including conventional buck, tapped-inductor buck and hybrid resonant buck converter, are compared. Finally, three hardware prototypes using gallium-nitride (GaN) devices with 24–48 V input and 3-A/5-V output are demonstrated and compared in terms of efficiency, size and thermal performance.

This paper, proposes the design approach to achieve fast transient response for the current-mode adaptive on-time control circuit of an on-chip buck converter. The major difference between the current-mode with and without adaptive on-time control circuits is the on-time generation circuit. The sample and hold transfer function of the current-mode adaptive on-time control circuit can obtain the fixed double poles system without a high Q at half the switching frequency. The current-mode adaptive on-time control circuit needs to design the current sense gain properly to obtain a large bandwidth with the appropriate phase margin to achieve a fast transient response. The 5-V input, 1.2-V and 1-A output on-chip buck converters with and without the current-mode adaptive on-time control circuit are implemented to verify the superiority of the adaptive on-time control through computer simulation and hardware experiments.

In this paper, improvement of the transient response of voltage-mode controller with the ripple-based circuit for an on-chip buck converter is proposed. The main purpose of the proposed circuit is to enhance the load transient response while maintaining the system stability. For the ripple-based circuit, a low-pass filter is used to generate a voltage signal similar to the inductor current waveform. This voltage signal is then injected into the voltage feedback with a bypass capacitor. Such a ripple-based control circuit can prevent instability caused by the output ceramic capacitors for buck converters. Because the voltage-mode controller does not require the current sensor, it can allow elimination of quiescent current caused by the current-mode controller and avoid the current sensor bandwidth limitation, which tends to result in high frequency distortion. This paper will discuss the design methodology of voltage-mode controller using ripple-based circuit for an on-chip buck converter. An on-chip 5-V input, 3.3-V and 1-A output ripple-based buck converter control is simulated and implemented with hardware prototype to verify the transient response improvement and stable operation during load step-up and - down dynamics.

A 12-pulse rectifier with the combination of $\Delta-\Delta$ and $\Delta-$ Y type phase-shift transformers has been commonly used for harmonic cancellation in a large-scale power system. Recently a shut phase-shift transformer was suggested to have the same harmonic cancellation effect with more than 75% size reduction over the traditional phase-shift transformers provided that the power generation system equips with multi-generator that can be regulated with 30° phase difference between the two sources. Theoretically, the harmonic trapping performance of a shunt configuration is equivalent to 12-pulse rectifier with a significantly reduced transformer rating and size. However, the working condition and the performance of a shunt phase-shift transformer rectifier under the practical condition have not been verified. This paper presents a detailed analysis of a harmonic elimination principle of a shunt phase-shift transformer through an equivalent circuit model and a mathematical derivation. The analysis also describes the working condition for a shunt phase-shift transformer rectifier and the effect of phase difference of generators on the harmonic cancellation performance. The derived model is verified with computer simulation under the ideal and non-ideal 30° phase-differential configurations.