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RFID plays a very important role as auto-identification solution for many industrial applications. In electric power industry, UHF RFID tags are attached on smart meters, and a tag provides a unique electronic identification for a smart meter, so RFID is applied to make asset inventory for smart meters in a warehouse. However, there are just about 95% of tags that are readable for their reader because of the interference of PCB and electronic components in smart meter, thereby it has to take a lot of time to manually find out the non-responsive tags. This paper puts forward a feasible method of testing tag's performance according to multi-tags group-reading environment in the application of smart meter asset inventory, and verifies the feasibility of the method through inventory experiments, and finally gives out an optimized parameters to read 100% of tags with the sensitivity of −16.25dBm in a multi-tags environment. The method is suitable for the test of large quantities of smart meters that are densely packed in a plastic box. The proposed method can guide electric power companies to select tags and readers, and improve the efficiency of inventory for smart meters asset management.

A 28 nm CMOS multistandard TV tuner is presented. A power-efficient RF front end and >80 dB dynamic range ΔΣ ADC, together with a smart AGC algorithm, enable this tuner to achieve 64 dB ATSC A/74 N+6 ACI while dissipating only 180 mW. A baseband resistor weighting harmonic rejection mixer clocked by a 7–13.6 GHz PLL and single-edge-triggered shift registers achieves >58 dB harmonic rejection ratio at frequencies up to 827 MHz.

A 28 nm CMOS Software-Defined Transceiver (SDTRX) enabling High-Speed Data (HSD) streaming, including Ultra HD TV, within home cable networks is presented. By making efficient use of available cable bandwidth, the SDTRX dynamically handles up to 1024QAM OFDM-modulated HSD streams. This paper addresses SDTRX system-level design methodology as the key driver in enabling performance optimization for achieving a wide frequency range of operation at the lowest power and area consumption. By employing an optimized architecture constructed on available state-of-the art 28 nm functional building blocks, the monolithic SDTRX consists of a mixer-based harmonic rejection RX with a DAC-based TX and a smart PLL system. It operates over a 0.4-to-1.7 GHz frequency range while consuming less than 475 mW in half-duplex mode. Moreover, by developing a simple TX-RX loopback circuit, the system is enabled to efficiently calibrate TX output power and to remove the need for a dedicated external pin. This low-cost SDTRX is embedded in various 28 nm CMOS multimedia SoCs and is, to the authors' knowledge, the first reported transceiver front end to enable true high-speed data streaming within home cable networks.

This work presents an integrated ultra high frequency (UHF), broadband direct-conversion receiver. The receiver integrates a single-ended RFVGA, an on-chip single-to-differential balun, a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. Targeted to operate between 470–862 MHz, the receiver achieves a noise figure of 7.9dB, an IIP3 of −8dBm at maximum gain and an IIP3 of +2dBm at 9dB RF attenuation. The gain- and frequency-programmable baseband section implements an 8th order inverse chebyshev low pass approximation achieving >42dB attenuation at an offset of 1.75 MHz for the 4 MHz frequency setting. Overall, the receiver consumes 120mW from 1.8V analog/2.5V digital dual supply and occupies 2.14mm2 in IBM 0.18/im RFCMOS technology.

The increased competition to deliver broadband data to the home (including GPON and VDSL) is motivating cable providers to deliver data rates which far exceed what is presently available based on the DOCSIS 1.x and DOCSIS 2.0 standards. The DOCSIS 3.0 standard provides this bandwidth increase as well as additional flexibility, where higher data throughput can be obtained by bonding together multiple downstream (DS) channels. This standard calls for the ability to bond any 4 channels in a 64MHz contiguous RF bandwidth. Solutions that allow even more channel bonding and provide more flexibility in the allocated frequency spectrum are preferred. This paper reports an embedded dual-tuner architecture able to select two independent 32MHz frequency bands, allowing for a maximum of 10 demodulated 6MHz Annex B DS channels. In Fig. 6.6.1 the top level block diagram is shown: an external LNA amplifies the RF signal which drives an internal splitter, followed by the two low-IF tuners. Each tuner downconverts 5 DS channels to IF frequencies centered at 0MHz (CH 0), +6MHz (CH +1), +12MHz (CH +2), −6MHz (CH −1) and −12MHz (CH −2). Channels +1 and +2 lie at the images of channels −1 and −2 respectively. Any or all channels can be selected for demodulation by the SoC, up to a maximum of eight. Image rejection is enhanced digitally, taking advantage of the tuner integration into the SoC.

A computer model-based approach is presented to characterize hemodynamic consequences of myocardial ischemia in terms of depressed ventricular elastance and delayed and reduced ischemic regional cardiac muscle shortening, as well as relaxation time constants. The model is shown to be versatile in quantitative assessment of the severity of myocardial ischemia.