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With the growing demand for satellite network technology in military and commercial applications, a large number of LEO(Low Earth Orbit) satellites have been launched in various countries around the world. One of the most important tasks is to download the data collected by these satellites to the Earth Stations(ESs) for processing. Previous research efforts have focused on how to download satellite-collected data to ESs. They didn't consider the situation that the satellites continuously collect data when downloading data. In this paper, our goal is to optimize the data download from the satellites to the ES in the case of dynamic collection of satellite data. We use inter-satellite links (ISLs) to offload data from heavily loaded satellites to the light ones. We build a topology map based on the interaction time between satellites and the interaction time between the satellite and the ES, and allocate the download time to the satellite carrying the largest amount of data. Then, the time slice is dynamically divided and the inter-satellite scheduling is determined by a way of classifying the idle satellites. Finally, the maximum flow algorithm is applied to determine the specific inter-satellite transmission scheme. In this way, the ES idle time is minimized. Simulations results show that our solution can greatly improve the data download efficiency from the satellites to the ES.

By changing the network topology or getting more state information, the convergence speed can increase, but it cannot be adjusted flexibly. In order to overcome this problem, we investigate the convergence speed adjustment problem of first order leader-following multi-agent systems. Firstly, we propose a γ-adaptive consensus protocol, where the weights of the edges can adaptively change according to the state difference between neighbouring agents. Then, a sufficient condition for consensus is given and the convergence speed is proved can be quantitatively adjusted through changing the value of γ approximately. Finally, numerical simulations are presented to illustrate theoretical results.

In this paper, we propose a novel denoising method combining wavelet analysis with compressed sensing for acceleration signal. The basic idea is that, in view of the wavelet coefficients with no noisy, the optimization reconstruction algorithm of compressed sensing is adopted to recover all new wavelet coefficients with no noisy from all selected wavelet coefficients, which contributes to further wavelet inverse transform for gaining clean acceleration signal. The acceleration signal from open database of USC-HAD is selected to validate the effectiveness of our proposed technique. The experimental results showed that, compared with the traditional wavelet threshold denoising methods, our proposed method can obtain the maximum SNR and minimal RMSE, and significantly improve the denoising performance of acceleration signal. These results demonstrate that our proposed technique take advantage of the sparsity of wavelet coefficients for enhancing the denoising ability of acceleration signal, which can overcome the limitation of threshold processing in wavelet analysis for denoising acceleration signal. Our work has a great potential for denoising other biomedical signals such as ECG, EEG and EMG.

A parameter optimization method based on relevance measurement in a prediction system is proposed. Meaning of dependency in parameter optimization is analyzed and reference standards of parameter optimization are proposed. This method is used in BP neural network to select the input parameter in a residual life prediction system of rechargeable batteries. The case study shows a good effect on initial parameter selection in a prediction system.

On the basis of the study of the analog electronic circuit theory, a component-level health quantitative assessment model based on support vector machine algorithm was proposed in this paper. This paper divided the health condition of analog electronic circuits into health status, sub-health status and failure status, then the particle swarm optimization (PSO) was applied on the optimization of support vector optimization parameters. In the end, this paper builds the component-level health quantitative assessment model based on support vector machine algorithm.

We propose a novel method that exploits BTI to partially offset variation and thus improve SRAM Vmin and yield. We show correlation between a bitcell's power-up state and its static noise margin. By applying stress with periodic re-power-up, device mismatch can be compensated by BTI induced changes. The proposed method has no extra design and area cost. It can be applied during burn-in test to offset manufacturing variation and/or used during the lifetime of the chip to offset variation from real-time aging and hence continue to improve the margins. Simulations in 45nm show that write, read, and hold Vmin at 6σ can be reduced by 128, 75, and 91 mV, respectively. Measurements from a 16Kb 45nm SRAM demonstrate the improvement of Vmin and yield.

Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. Large scale 6T SRAM arrays beyond 65nm will increasingly rely on assist methods to overcome the functional limitations imposed by increased variation, reduced overdrive and the inherent read stability/write margin trade off. Factors such as reliability, leakage and data retention establish the boundary conditions for the maximum voltage bias permitted for a given circuit assist approach. These constraints set an upper limit on the potential yield improvement that can be obtained for a given assist method and limit the minimum operation voltage (Vmin). By application of this set of constraints, we show that the read assist limit contour (ALC) in the margin/delay space can provide insight into the ultimate limits for the nano-scale CMOS 6T SRAM.

WiMAX is one of the most promising technologies which is to go through wireless broadband last mile access. Handover procedure plays a crucial role in the mobile WiMAX application. This paper introduces an implementable enhanced handover target cell selection algorithm for WiMAX network based on the effective capacity estimation and neighbor advertisement which can effectively avoid the ping-pong effect and handover synchronization effect. NS-2 simulation is also given to show the performance enhancement of the enhanced algorithm compared with the traditional algorithm based on signal power and 802.16g quick handover algorithm.

This paper examines the impact of technology scaling to 22nm on sub-threshold circuit design and proposes several solutions for sub-threshold circuits in new processes. To maintain energy-efficient sub-threshold operation, we must reduce variation and suppress leakage current. To combat random variation and minimize energy for nodes below 45nm, we show that special strategies are needed for different categories of sub-threshold circuits.

In the process of the image information hiding, the secret image should be pretreated by used of chaos sequences which are produced by chaos system, in order to improve the robustness of the algorithm. Some popular algorithms can be utilized to solve it, for example, the Logistic map could produce the chaos sequences to complete the image pretreated. But, the security of the unidimensional chaos system is weak because the system is a common chaotic encryption system. In this paper, a compound encryption algorithm of a double unidimensional chaos system is recommended according to the ten-thousand-year experience of human, the algorithm is designed by used of two unidimensional chaos sequences to encrypt the places and grey of the pixels respectively. In order to implement the information hiding in wavelet domain conveniently, the algorithm is based on non-uniform B-spline wavelet. The experiments testify that this algorithm possessed the merit of strong robust and drawing blindly.

Circuit reliability under statistical process variation is an area of growing concern. For highly replicated circuits such as SRAMs and flip flops, a rare statistical event for one circuit may induce a not-so-rare system failure. The Statistical Blockade was proposed as a Monte Carlo technique that allows us to efficiently filter-to block-unwanted samples insufficiently rare in the tail distributions we seek. However, there are significant practical problems with the technique. In this work, we show common scenarios in SRAM design where these problems render Statistical Blockade ineffective. We then propose significant extensions to make Statistical Blockade practically usable in these common scenarios. We show speedups of 102+ over standard Statistical Blockade and 104+ over standard Monte Carlo, for an SRAM cell in an industrial 90 nm technology.

This paper presents two fast and accurate methods to estimate the lower bound of supply voltage scaling for standby SRAM/cache leakage power reduction of an SRAM array. The data retention voltage (DRV) defines the minimum supply voltage for a cell to hold its state. Within-die variation causes a statistical distribution of DRV for individual cells in a memory array, and cells far out the tail (i.e. >6sigma) limit the array DRV for large memories. We present two statistical methods to estimate the tail of the DRV distribution. First, we develop a new statistical model based on the connection between DRV and static noise margin (SNM). Second, we apply our Statistical Blockade tool to obtain fast Monte-Carlo simulation and a generalized Pareto distribution (GPD) model for comparison. Both the new model and the GPD model offer a high accuracy ( 104times for 1 G-b memory) over Monte-Carlo simulation. In addition, both models show a very close agreement with each other at the tail even beyond 7sigma.

Canary bitcells act as online monitors in a feedback architecture to sense the proximity to the data retention voltage (DRV) for core SRAM bitcells during standby voltage scaling. This approach implements aggressive standby VDD scaling by tracking PVT variations and gives the flexibility to tradeoff between the safety of data and decreased leakage power. A 90 nm 128 Kb SRAM test chip confirms that the canary cells track changes in temperature and VDD and that they provide a reliable mechanism for protecting core cells in a closed loop VDD scaling system. Power savings improve by up to 30times compared with the conventional guard-banding approach.

This paper reports a 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18 mm 1.8 V 1P6M logic CMOS technology. This cache is designed for a 32-b RISC microprocessor. Effective latency of 3.4 ns and power consumption of 190 mW at 263 MHz are obtained at a supply voltage of 1.8 V. This performance is achieved by using high speed circuit design techniques such as modified high speed current-mode sense amplifier and split dynamic tag comparators.