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This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (Ultra- Wideband) application using 0.13 um CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz, 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and prescaler architecture are also presented in this paper. A new coarse tuning scheme that utilizes the MIM capacitance and the varactor is proposed to expand the VCO tuning range. The single PLL and two SSB-mixers consume 75 mW from a 1.5 V supply. The VCO tuning range is 500 MHz. The simulated phase noise of the VCO is -110 dBc/Hz at 1 MHz offset. The die area is 3 times 2 mm2.

This paper presents a sigma-delta modulation ADC(analog-to-digital converter) and DAC(digital-to-analog converter) for CODEC applications using 0.18 um CMOS process. In the ADC parts, two sigma-delta modulators with 84 dB SNR are designed for the stereo applications, and their outputs are merged at the digital domain before decimation filter. Digital decimation filter is integrated with the analog sigma-delta modulators for the full ADC operation. In the DAC parts, the digital data is first processed at the interpolator filters, and modulated by the following sigma-delta modulators. To reduce the mismatch effect of the following DAC, the dynamic element matching method is proposed in this paper. It is designed with 0.18 mum CMOS process. The simulated SNR is about 100 dB, and the power consumption is 40 mA.

This paper presents a σ-δ modulation ADC (analog-to-digital converter) and DAC (digital-to-analog converter) for CODEC applications using 0.18 μm CMOS process. In the ADC parts, two σ-δ modulators with 84 dB SNR are designed for the stereo applications, and their outputs are merged at the digital domain before decimation filter. Digital decimation filter is integrated with the analog σ-δ modulators for the full ADC operation. In the DAC parts, the digital data is first processed at the interpolator filters, and modulated by the following σ-δ modulators. To reduce the mismatch effect of the following DAC, the dynamic element matching method is proposed in this paper. It is designed with 0.18 μm CMOS process. The simulated SNR is about 100 dB. and the power consumption is 40 mA.

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (Ultra-Wideband) application using 0.13 um CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz, 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and prescaler architecture are also presented in this paper. A new coarse tuning scheme that utilizes the MIM capacitance and the varactor is proposed to expand the VCO tuning range. The single PLL and two SSB-mixers consume 75 mW from a 1.5 V supply. The VCO tuning range is 500 MHz. The simulated phase noise of the VCO is -110 dBc/Hz at 1 MHz offset. The die area is 3 x 2 mm2.

This paper presents a baseband complex bandpass filter for PHS applications with a new automatic tuning method. The full-CMOS PHS transceiver is implemented by adopting the Low-IF architecture to overcome the DC-offset problems. To meet the adjacent channel selectivity (ACS) performance, the 3rd-order Chebyshev complex bandpass filter is designed as the baseband channel-select filter. The new corner frequency tuning method is proposed to compensate the process variation. This method can reduce the noise level due to MOS switches. The filter was fabricated using a 0.35 mum CMOS process, and the power consumption is 12 mW.

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about 20 mus and the phase noise is - 121dBc/radicHz at 600kHz offset. This chip is fabricated with 0.25mum CMOS technology, and the die area is 0.7mm times 2.1mm. The power consumption is 54mW at 2.7V supply voltage