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A SDH overhead terminator chip set has been designed for 10 Gbit/s optical transmission system. The chip set built on 0.6 /spl mu/m CMOS technology and 0.6 /spl mu/m H-GaAs III MESFET technology successfully realizes the functions needed for regenerator section termination and multiplex section termination with alarm detection and generation, and performance monitoring. This paper introduces a novel multiplexing structure for parallel processing of the STM-64 frame signal and describes the architecture of the chip set.

We propose a new interference cancellation scheme called the symbol-by-symbol based adaptive interference canceller (SAIC). The SAIC adaptively estimates and removes both multiple access interference (MAI) and intersymbol interference (ISI) at the output of the RAKE receiver. It requires neither respreading nor the evaluation of partial cross-correlation. In addition, its complexity is independent of the number of fingers of the RAKE receiver. Consequently, the SAIC is considerably simpler to implement than existing techniques. Computer simulation results demonstrate that the SAIC can perform much better than a conventional RAKE receiver.

A full section overhead (SOH) processing chip set has been designed for use in a 10 Gbit/s SDH-based optical fiber transmission system. The chip set has been fabricated in a 0.6 /spl mu/m CMOS and GaAs gate array technology. The features supported by the chip set include STM-64 SOH insertion and extraction including regenerator section trace (RST), frame alignment word insertion and detection, 32-bit parallel scrambling and descrambling, 8:1 multiplexing and demultiplexing, alarm detection and generation, and performance monitoring. This paper introduces a novel multiplexing and demultiplexing structure for a parallel processing of the STM-64 signal using the chip set. This paper also describes the architecture of the chip set, and several of the chip set's more interesting features.

We conducted a transmission experiment using MB34 line coded data with a 10 Gb/s optical transmission system to see if this code could be used as an alternative line code for high speed optical transmission. The test results showed that the transmission distance could be lengthened when the minimum-bandwidth line code was used and the eye pattern and power spectral density were coincident with the expected shapes. The timing jitter, S/N, and receiver sensitivity were improved 12 ps, 3.2 dB, and 1.3 dB, respectively. With these results, the MB34 data can lengthen the transmission distance by longer than 5 km compared with conventional NRZ data.

A Unique CMOS Section Overhead (SOH) processor has been designed for use in 10 Gbit/s SDH-based optical transmission system. A uniquely structured chip makes it possible to use parallel processing of STM-64 SOH at low speed with four identical chips. The features supported by the chips include STM-64 SOH insertion and extraction including Regenerator Section Trace (RST), frame alignment word insertion, alarm detection and generation, and performance monitoring. This paper introduces a novel parallel circuit design methodology for processing STM-64 SOH and describes the unique architecture, implementation and experimental test results of the chip, SOH processor. This paper also presents the implementation methodology of RST using CRC-7 polynomial algorithm.