Search

The increasing connectivity of devices in our daily lives has driven the need for higher bandwidth in network and data centers. Recently, we have seen the development of 112Gb/s SerDes, particularly for long-reach interfaces [1– 3]. In high-density switch ASICs, we see an increasing demand to improve both area efficiency (mm2/lane) and signaling efficiencies (pJ/b) [1– 6]. In a switch ASIC, keeping the SerDes power low translates into broader system power savings since additional power and cost for cooling can be limited or even avoided entirely. One path forward to achieve these important system gains is co-packaged optics (CPO) with an extra-short-reach (XSR) interface. In these applications the switch ASIC and optical engine are no more than 50mm apart which represents a total loss of approximately 10dB at 106.25Gb/s.

The scaling of CMOS technology together with continued innovations in circuit and system design techniques is fueling a rising demand for increasingly high throughput serial data interfaces. However, advances in CMOS technology have little impact on channel performance, making channel impairments a bottleneck in wireline links. Furthermore, links are typically designed to cover multiple standards and are expected to operate over a wide range of data rates, making their design challenging [1-5]. This work presents a 4-lane 1.25–28.05Gb/s transceiver in 14nm FinFet technology. We measure a bit error rate (BER) lower than 1e-15 with a channel loss of 40dB at 28.05Gb/s.

A small form-factor 60-GHz SiGe BiCMOS radio with two antennas-in-package is presented. The fully-integrated feature-rich transceiver provides a complete RF solution for mobile WiGig/IEEE 802.11ad applications.

The bandwidth limitation of existing backplanes has become an obstacle to meeting the increasing demand for high-data-rate wireline transmission. In order to compensate for this limitation, TX pre-emphasis, RX continuous-time linear equalizer (CTLE) and DFE are necessary [1,2]. This work presents a 4-lane transceiver implemented in 40nm CMOS technology that operates over a wide range of data rates from 1 to 12Gb/s (48Gb/s aggregated) using NRZ coding. The supply voltages are 0.9V and 1.8V. An algorithm is developed to adapt the CTLE and DFE to cancel the channel ISI. No inductors are used in the design and ring oscillators are used for both the TX and RX clock generation. This provides a wide frequency-tuning range, small layout area, and high design portability. With extensive use of digital programmability this transceiver is capable of meeting specifications of different standards, such as PCIe, SATA, and 1 to 10Gb/s Ethernet.