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In this paper we propose a new architecture of the self-organized body schema (SO-BoS) system capable of learning the configuration space of three rotorcrafts relative to a single sensor space. The SO-BoS cortical map architecture represents the posterior parietal cortex where sensory-motor of the human posture is synthesized (circular-reaction); we inspired on such process to control the displacement in formation of three rotorcraft UAVs. The SO-BoS-based feedforward control drives the aerial robots formation towards the desired position while avoiding obstacles and inter-agent collisions. The proposed strategy is a promising approach for aerial vehicles systems due to the plasticity resulting from the learning-babbling stage. A numerical result section is given to provide the inherent discussions to assess the effectiveness of the proposed intelligent navigation scheme.

integration requires development of low thermal budget process modules. High-quality SiO 2 interfacial layer (IL), obtained up to now only by high-temperature (≥850°C) oxidation or exposure, is crucial for pMOS NBTI reliability. In unannealed IL’s grown at reduced temperatures, we show that unrelaxed interface strain induces high defect densities, with physics-based NBTI modeling suggesting excessive hydroxyl-E’ defect formation due to Si-O bond stretch. Based on ab-initio theoretical insights, we demonstrate an atomic hydrogen treatment to passivate SiO 2 defects at low temperatures (100-300°C), which is shown to be vastly more effective than high pressure molecular hydrogen exposure, and to yield an SiO 2 quality and reliability surpassing a 900°C oxide.

We demonstrate multiple ways to reduce the D IT of Si-cap-free low-Ge-content (25-30%) SiGe gate stack. The D IT is reduced by i) Ge oxide scavenging via Ge condensation or by the work function metal (WFM), ii) nitridation of gate dielectrics and iii) optimized high-pressure anneal (HPA). A moderate nitridation of the interface layer (IL) is beneficial in EOT and D IT reduction, while nitridation of the HfO 2 dramatically reduces D IT by negating an ALD TiN-induced D IT increase. The optimized gate stack is evaluated in 8-nm-wide strained Si 0 7 Ge 0 3 pFinFETs integrated on 300 mm Si wafers, for which a 35% improvement in high-field mobility is demonstrated as compared to Si pFinFET counterparts.

We have validated that the electrical performances of the In0.53Ga0.47As MOSFETs such as sub-threshold slope (SS) and electron mobility were dependent on interfacial reactions in the metal/highk/InGaAs gate stacks which could be controlled remotely by choice of the metal electrodes. We demonstrated In0.53Ga0.47As MOSFETs with high mobility (peak mobility ~1300 cm2/Vs) and superior SS performance (SS 76.4 mV/dec) at the scaled CET region owing to the remote reduction of the native III-V oxide by the TiN electrodes.

Fin height dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high-κ metal gate (HKMG) FinFETs transistors is reported for the first time. It was observed that NBTI degradation is less severe when increasing the physical height of the silicon fin. The increased fin height results in a lower effective defect density, believed to be related to a reduced role of the defective fin corners and/or top surface. PBTI results reveal a similar, albeit less severe, impact of fin height, suggesting an impact of fin height on the high-κ layer, with again an increased defectivity at the fin corners and/or top surface, whose effective role is reduced in the case of taller fin.

3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the $I_{ON}$ performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.

Low thermal budget gate stacks will be required for novel integration schemes, such as 3D sequential stacking of CMOS tiers. We study the impact of a reduced thermal budget on BTI reliability, and we demonstrate interface dipole engineering to suppress the carrier-defect interaction and achieve sufficient nMOS PBTI and pMOS NBTI reliability without the customary post-deposition anneals.

Degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD), as well as the associated time-dependent variability, dictate the limit on the acceptable operating voltage conditions in modern deeply-scaled VLSI devices. Based on large statistical datasets, acquired using specifically designed on-chip arrays, we experimentally obtain DC degradation maps for both $\boldsymbol{n}$ - and $\boldsymbol{p}$ -type FETs. Defect-centric based analysis of the statistical parameters at every $\boldsymbol{V_{G}}, \boldsymbol{V_{D}}$ bias point provides physical insights in the underlying single- and multi-carrier degradation processes. As a result, we can separate the defect charging contributions of each degradation mechanism and describe to which extent these mechanisms co-interact. We finally present a simplified model (the “3-bucket” model) that is able to describe the degradation statistics up to $3\boldsymbol{\sigma}$ of a device population subject to an arbitrary combination of BTI and HCD stress.

Potential solutions for the reliability challenges of high- k metal gate (HKMG) integration into DRAM high-voltage peripheral logic devices are reported. A detailed study of Negative Bias Temperature Instability (NBTI)-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high-k fluorination and/or cap, metal gate) is presented. The presence of Nitrogen throughout the HKMG stack can originate either from high-k processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO 2 interface region, together with AIO x (and F) incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance.

This document describes a signal processing technique to reconstruct the high-frequency current of a DDR4 DIMM at BGA level, by using the current measured at a remote shunt resistor.Simulation results using the reconstructed current show very good correlation with experimental data, proving that the proposed approach is an accurate, reliable low-cost low-complexity characterization technique.

Low thermal budget gate stacks will be required for novel integration schemes, such as 3D sequential stacking of CMOS tiers. We study the impact of a reduced thermal budget on BTI reliability, and we demonstrate two strategies to tolerate the inherently large high-k defect densities: i) replacing inversion mode devices with highly doped junction-less transistors, or ii) engineering dipoles at the interface between SiO 2 and HfO 2 to suppress the carrier-defect interaction. The latter approach is demonstrated for nMOS PBTI and, for the first time here, also for pMOS NBTI, as even this aging mechanism is controlled by high-k defects in ultra-thin EOT low thermal budget gate stacks.

3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(\mathrm{T}\leq 525^{\circ}\mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature.

In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Junction-less devices are shown to be attractive top tier devices for low temperature processing, low complexity of fabrication and meeting reliability specification despite without the use of “reliability” anneal. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.

In modern VLSI devices, a multitude of degradation mechanisms dictates limits on the tolerable voltage conditions to guarantee reliable operation for extended times. The most critical degradation mechanisms such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD) are mostly studied in terms of their mean degradation. By obtaining large statistical datasets, covering a multitude of conditions in the {V G ,V D } bias space, typically obtained by measurements on dedicated on-chip FET arrays, we show that we can identify the active degradation mechanisms and understand their impact on both FET time-zero metrics, as well as on the time-dependent variability.

We investigate BTI charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals. Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the metal work function. However, experimental data show enhanced or reduced charge trapping at constant oxide electric field for different work function metal stacks. We ascribe this to a different chemical interaction of the metal stack with the dielectric, yielding different defect profiles depending on the process thermal budget. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy”, we also show that different metal work functions within a typical range of relevance (4.35-4.75eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs.

Malicious traffic has garnered more attention in recent years, owing to the rapid growth of information technology in today’s world. In 2007 alone, an estimated loss of 13 billion dollars was made from malware attacks. Malware data in today’s context is massive. To understand such information using primitive methods would be a tedious task. In this publication we demonstrate some of the most advanced deep learning techniques available, multilayer perceptron (MLP) and J48 (also known as C4.5 or ID3) on our selected dataset, Advanced Security Network Metrics & Non-Payload-Based Obfuscations (ASNM-NPBO) to show that the answer to managing cyber security threats lie in the fore-mentioned methodologies.

In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.

Charge trapping in the gate-oxide can cause significant degradation and reduce the operating lifetime of the device. Here, we study the kinetics of charge trapping in the InGaAs/Al 2 O 3 /HfO 2 gate-stack using Capture and Emission Time (CET) maps. The existence of two oxide defect bands, respectively above and below the conduction band of InGaAs, is implied by sensing charge trapping at positive and negative oxide electric fields. Within each band, two distinct populations of defect states are observed. The first defect population with relatively higher capture and emission energy barriers is found to affect the long term reliability of the device since the charge trapping in these defect states is slow, while the second population with relatively smaller capture and emission energy barriers affects the device stability particularly under high frequency operation. We argue that it is essential to characterize and study both defect populations in order to accurately estimate device lifetime under different operating applications.

Time-dependent variability of modern VLSI devices, due to their associated degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD), dictates a limit on the tolerable operating voltage conditions of the device. Based on a large statistical dataset, obtained by measurements on dedicated on-chip FET arrays, we propose a methodology to identify and de-convolute the active degradation mechanisms and subsequently calculate the respective lifetimes in bias {Vg, Vd} space. Utilizing a limited set of parameters for each of the identified failure mechanisms, we show excellent agreement with experimental degradation data over the entire measurable bias space. Finally, by experimental assessment of thermal resistance and degradation activation energies, we can project a self-heating-aware FET lifetime at operating conditions across the entire bias space.

We study hot carrier degradation in Si 0 . 75 Ge 0 . 25 p-FinFETs by measuring degradation maps in the entire bias space and compare with Si counterparts. Hot carrier effects are found to be exacerbated in SiGe due to the reduced impact ionization threshold in small bandgap semiconductors, the larger hole mean free path, and the consequently enhanced generation of secondary electrons. Both hole and electron injections are observed and they partially compensate each other at some stress biases. Even at operating voltages of relevance for core logic applications, off-state stress causes an increased channel off-state leakage due to hot-electron-induced punch-through.

This work presents an impedance vs coupling noise analysis for Power Delivery (PD) interconnection at the package (PKG) level. The work is focused on power rails that supply multiple loads from a single power source. The analysis and design process presented for mitigating the coupled noise on sensitive domains is based only on PKG power routing layout. The analysis and design method documented has been used on the Power Delivery Network (PDN) for Intel's Xeon Phi server platforms.

We review our recent studies of oxide traps in InGaAs MOS gate stacks for novel high-mobility n-channel MOSFETs. We discuss and correlate various trap characterization techniques such as Bias Temperature Instability, defect Capture-Emission-Time maps (applied here to InGaAs devices), Random Telegraph Noise, hysteresis traces, multi-frequency C-V dispersion, all performed on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). Finally we demonstrate guidelines for developing sufficiently reliable IIIV gate stacks.

This paper considers a multiple integer non-linear programming model that aims to optimize the three types of bundling strategies while considering the selection of components for the bundles that integrates the degree of contingency and the dead stock component of the product. The proposed model is validated through different scenarios with varying incremental input parameters in order to determine the effects of the variables to the objective function and the sensitive points in the model. The results were able to show that an increasing degree of contingency is able to affect the pure component variable while the interaction of degree of contingency and the reservation price of a mixed individual appears to have a significant effect on the number of pure bundles. In addition, the dead stock level and degree of contingency have produced adverse effects to bundling optimization. These results have shown that integrating component selection, dead stock level and bundling strategies gave the model the flexibility to change through its varying parameters improving its profitability.

In this paper, we demonstrate for the first time an implant free In 0.53 Ga 0.47 As n-MOSFET that meets the reliability target for advanced technology nodes with a max operating V ov of 0.6 V. In addition, an excellent electron mobility (μ eff, peak =3531 cm2/V-s), low SS lin =71 mV/dec and an EOT of 1.15 nm were obtained. We also report the scaling potential of this stack to 1nm EOT without loss of performance, reliability and further reduction of the sub-threshold swing (SS lin =68mV/dec). On top of the novel IL we presented last year, in this paper we insert a LaSiO x layer between the IL and HfO 2 offering an increased chemical stability of the gate stack. This combination is key and offers both an improved interface quality as well as a reduction of the oxide trap density.

This paper presents a method to characterize the power delivery network impedance seen at the silicon level in a high speed I/O interface using pseudorandom bit stream (PRBS) patterns. Moreover, results from a transient simulation using the extracted impedance are compared with laboratory measurements, showing good correlation.

Time-dependent variability of junctionless gate-all-around nanowire pFETs is studied through measurements and simulations. The variability, related to effects such as Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI), is discussed in terms of the distribution of individual charged gate oxide trap threshold voltage shifts. This distribution is shown to be shaped by i) the electrostatics of the device, and ii) percolative source-drain conduction. It is concluded that the time dependent variability of our JL GAA NW pFETs is comparable to previously measured pFinFETs. However, provided that other sources of variability are suppressed, JL FETs time-zero and time-dependent variability may remain high due to the high body doping.

Instabilities in MOS-based devices with various substrates ranging from Si, SiGe, IIIV to 2D channel materials, can be explained by defect levels in the dielectrics and non-radiative multi-phonon (NMP) barriers. However, recent results obtained on single defects have demonstrated that they can show a highly complex behaviour since they can transform between various states. As a consequence, detailed physical models are complicated and computationally expensive. As will be shown here, as long as only lifetime predictions for an ensemble of defects is needed, considerable simplifications are possible. We present and validate an oxide defect model that captures the essence of full physical models while reducing the complexity substantially. We apply this model to investigate the improvement in positive bias temperature instabilities due to a reliability anneal. Furthermore, we corroborate the simulated defect bands with prior defect-centric studies and perform lifetime projections.

3D Sequential integration has been envisioned to stack transistors in the same front-end process. A crucial challenge is the management of the thermal budget. This work focuses on Si nMOS gate stack challenges, specifically: for a top tier device, by inserting a thin LaSiO x interlayer between SiO 2 and HfO 2 a sufficient PBTI reliability is demonstrated without resorting to unsuitable high temperature anneals. This gate stack also offers good thermal stability for a pMOS over nMOS scenario.

This work analyzes the data output of laser ranging data collected from the SGF (Herstmonceux, UK), and proposes a bespoke likelihood function for its processing in the context of Bayesian filtering. It is then illustrated in a single-target Bayesian filter, performing successfully on simulated and real data, under a variety of noise profiles encountered in typical outputs of the sensor.

CMOS technology scaling to decananometer range has raised the challenge to mitigate the impact of multi-scale process variations ranging from cm to atom-scale and acting as circuit yield detractors. Moreover, circuit applications in Ultra Low Power (ULP) range lead to MOSFET device operation in near threshold regime where it is well established that variability impact on DC/AC electrical characteristics dramatically increases. Variability mitigation techniques are part of process development. In addition, accurate circuit design methodologies are required to determine circuit performance margins versus specifications, and to develop circuit level variability mitigation/compensation techniques, to enable high yield and manufacturable products in presence of variability. In this context, we update device modeling requirements for circuit design, revisit device electrical characterization and compact modeling methodologies needed to support accurate circuit simulation throughout the design space. We focus on spatial variability components at local scale, including systematic layout effects and statistical variability. This approach is illustrated on UTBB FDSOI devices. Device modeling challenge for accurate circuit simulation in presence of variability is better identified.

This paper presents an experimental study of the sensitivity to 14-MeV neutrons to low bias voltage of a COTS 90-nm Cypress SRAM. Experiments involving power supplies ranging from 0.5V to 3.3V are presented and discussed. These results have also been compared with cross-section and SER theoretical predictions.

International audience; Recently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Field Programmable Gate Arrays (FPGAs) and the original authors indicate that it is also valid for SRAMs. This paper presents a modified methodology that is based on checking the XORed addresses with bitflips, rather than on the difference. Irradiation tests on CMOS 130 & 90 nm SRAMs with 14-MeV neutrons have been performed to validate this methodology. Results in high-altitude environments are also presented and cross-checked with theoretical predictions. In addition, this methodology has also been used to detect modifications in the organization of said memories. Theoretical predictions have been validated with actual data provided by the manufacturer.

Vertical nanowires and for the first time vertical fins, dry etched from the same lattice matched InGaAs on InP, are used to fabricate MOSFETs. Single and multiple pillar array devices exhibit excellent electrostatics with min SS = 68mV/dec (V DS =0.05V) and max G m = 580µS/µm (V DS =0.4V). These are the first IIIV pillar array devices fabricated with top-down approach. Linear I on scaling with effective width and overall V th uniformity makes this result the first step in assessing the manufacturability of this integration scheme. A reliability analysis puts these vertical MOSFETs in line with other IIIV devices with similar gate stack, indicating that the IIIV etch does not introduce additional interface defects.