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A simultaneous wideband input/output matching technique for ultra-wideband (UWB) low-noise amplifier (LNA) is proposed in this paper. Feedback resistors leading the gate inductors combined with inductive dividers at output ports achieve an extended bandwidth and good input/output return loss. Moreover, $Q$ -factor improved vertical solenoid inductors are used in the matching networks for high gain and low noise figure (NF). The proposed matching technique, not only enhances the bandwidth, but also achieves a high gain and a low NF for the fabricated 3.1-10.6-GHz monolithic 180-nm CMOS UWB amplifier. Operating at low supply voltage, the measured power consumption is 18.9 mW, the measured gain of the UWB LNA is 15.02 dB, and the NF is 3.1 dB. Moreover, the measured input/output reflection coefficients S11 and S22 are lower than −9.4 dB and −15.8 dB, respectively, covering the full-band UWB frequencies. Compared to previously published full-band 3.1-10.6-GHz 180-nm CMOS UWB LNAs, the proposed LNA measurements demonstrate high gain, low NF, low supply voltage, low power dissipation, and good input/output reflection coefficients.

Virtualization is widely used in modern computer systems ranging from personal computers to cloud servers as it provides various heterogeneous platforms at low cost. However, due to its nested software structure in host and guest machines that are difficult to harmonize, it is challenging to manage resources efficiently in virtualized systems. In this article, we anatomize the overhead of virtualization associated with file system journaling and discover the excessively frequent commits that take place in virtualized systems. This is because the host triggers commit on every write request from all guest machines. This also generates unnecessary write traffic to storage. To remedy these problems, we propose the VM-separated commit, and implement it on QEMU-KVM and Ext4. Specifically, we devise a data structure that manages modified file blocks from each guest as a separate list and split the running transaction list into two sub-transactions based on this data structure upon a commit request from a guest. Measurement studies with Filebench and IOzone benchmarks show that the proposed policy improves the I/O throughput by 19.5% on average and up to 64.2% over existing systems. It also reduces the variability in performance.

The article presents a successful implementation of the milling process simulation at the Field-Programmable Gate Array (FPGA). By using FPGA, very rigorous Real-Time (RT) simulation requirements can be met. The response time of the FPGA simulations is significantly reduced, and the time synchronization is better than in a typical RT system implemented in software. The FPGA-based approach is characterized by enormous flexibility when it comes to input and output operations that can be implemented deterministically in RT. Complex simulation software has been implemented using the High Level Synthesis technique, which is a relatively easy and fast approach for FPGA programming without using complex Hardware Description Languages. The hardware functions are based on procedures written in high-level C programming language. The mathematical descriptions of simulations, results of computer simulations, Hardware-in-the-Loop Simulation experiments, and real experiments are presented. The approach presented in this paper can be used to simulate the dynamics of various mechatronic systems.

In this paper, we analyze I/O log data monitored in the Windows operating system for improving the system performance. Especially, we focus on the I/O operations to the Windows registry. As a result, we identify redundant access patterns of the Windows applications. To find all the possible redundant patterns from the large-scale log data, we propose the redundancy detection algorithm. Then, we propose the two-level redundancy elimination method to remove unnecessary redundant operations. We also present an event-driven method that guarantees that the result of redundancy elimination is equivalent to that of the original program. Through experiments, we show that the proposed redundancy elimination method improves the performance of the original program having redundant access patterns by up to 90.25% for individual access patterns; by 8.93% ~ 26.21% when the multiple programs having combined access patterns are running concurrently.

To effectively compute convolutional layers, a complex design space must exist (e.g., the dataflow techniques associated with the layer parameters, loop transformation techniques, and hardware parameters). For efficient design space exploration (DSE) of various dataflow techniques, namely, the weight-stationary ( WS ), output-stationary ( OS ), row-stationary ( RS ), and no local reuse ( NLR ) techniques, the processing element (PE) structure and computational pattern of each dataflow technique are analyzed. Various performance metrics are calculated, namely, the throughput (in giga-operations per second, GOPS), computation-to-communication ratio ( CCR ), on-chip memory usage, and off-chip memory bandwidth, as closed-form expressions of the layer and hardware parameters. In addition, loop interchange and loop unrolling techniques with a double-buffer architecture are assumed. Many roofline model-based simulations are performed to explore relevant dataflow techniques for a wide variety of convolutional layers of typical neural networks. Through simulation, this paper provides insights into the trends in accelerator performance as the layer parameters change. For convolutional layers with large input and output feature map ( ifmap and ofmap ) widths and heights, the GOPS of the NLR dataflow technique tends to be higher than that of the techniques. For convolutional layers with low weight and ofmap widths and heights, the RS dataflow technique achieves optimal GOPS and on-chip memory usage. In the case of convolutional layers with small weight widths and heights, the GOPS of the WS dataflow technique tends to be high. In the case of convolutional layers with small ofmap widths and heights, the OS dataflow technique achieves optimal GOPS and on-chip memory usage.

Computational application demands do push the scaling of the number of cores, which themselves further increase the demand for more bandwidth. The use of larger rank widths and/or scaling the number of memory controllers (MCs) is a straightforward way to increase memory bandwidth. Connecting wide ranks and MCs via low-capacitance Through Silicon Vias (TSVs) favors high-bandwidth 3DStacking systems (e.g. Wide I/O). Given that voltage and frequency scaling (VFS) lower power utilization but the use of lower clock frequencies reduces bandwidth, this article proposes $Walter$ as a $W$ ide I/O technique that trades off sc $al$ ing of the number of memory con $t$ roll $e$ rs (MCs) versus clock $\text{f}r$ equency and voltage (VFS) to mitigate low bandwidth and improve energy-per-bit usage. Our findings show that $Walter$ ’s Wide I/O architectural benefits of using a larger number of MCs coupled with wider ranks when combined to VFS are promising: compared to the baseline for a 75% frequency/voltage reduction, MC scalability improved memory bandwidth by 2.4x and energy-per-bit reduced by 20% (most benchmarks for up to 16 MCs). $Walter$ ’s architectural replacement of ranks set at specification frequencies with ones set at lower frequencies allows temperature reduction thus likely allowing further rank stacking.

In asynchronous quasi delay-insensitive (QDI) circuits, temporal masking is a serious concern because of their event-driven behavior, which makes them prone to environmental effects: Data acceptance windows, e.g. are defined by transitions (token/acknowledgement) alone, without temporal bounds, therefore a glitch occurring anytime throughout such a window cannot be distinguished from an expected, correct transition in a straightforward manner and hence threatens data integrity. Therefore, shortening that window is one proposed way in the literature to enhance temporal masking in QDI designs.We examine a variant of the Weak-Conditioned Half Buffer (WCHB) called Interlocking WCHB (which wisely shortens the transition window) because of its glitch filtering properties and a low cost implementation as compared to other variants. We propose modifications that enhance its dealing with illegal token words specifically when waiting for acknowledgment signal transitions in the so-called bubble limited operation mode. A very strict triple-check input filter with a glitch filter preventing the buffer from capturing an illegal state is used, which also enhances the deadlocking rate of the circuitry.

Virtual machine (VM) is an isolated domain that gives off an impression of being an entire PC yet in reality just approaches a bit of the PC assets. Execution of the virtual machine running on a similar PC framework equipment relies upon the exhibition of the host working framework. In this work execution of various visitor VM's on a similar host working framework has been analyzed. Here in this detailed experimentation or comparative analysis, Ubuntu, a Linux based operating system has been utilized for host working framework and for guest working frameworks Ubuntu v14.04, CentOS v6.3 operating systems has been utilized. Execution estimation of virtual operating system has been completed in the equivalent controlled scenarios for both (Ubuntu and Centos) guest operating systems utilizing benchmark applications. In this paper Input Output file operations have been performed on various virtual machine using benchmarking tool (Sysbench) to analyze the performance of various guest (Visitor) VM and compare them.

"Tour Pin Input Output" (FPIO) is a delayinsensitive asynchronous bit-serial multi-chip management protocol which surpasses "Serial Peripheral Interface" (SPI) by eliminating timing races, waiting for peripherals to acknowledge, using unidirectional fanout-1 full-swing signals, eliminating chip select wires, and scaling to rings of dozens of chips using less wiring. The message protocol over FPIO supports on-chip tree and ring topologies to connect internal interfaces such as virtualized wires, scan chains, NoC message interfaces, and circuit testers. Intel’s Loihi neuromorphic processor and related chips use this new infrastructure. We propose these protocols as an open standard for serial management, especially suited for asynchronous chips.

Preliminary study of a TE20 input/output coupling structure for sheet electron beam traveling wave tubes is presented in this paper. A TE10-TE20 mode converter and a single branch waveguide coupler are used to realize the proposed design. Simulation results obtained by using the CST simulation software demonstrated that the port reflection and the transmission coefficient were respectively lower than - 15 dB and higher than - 1 dB in the frequency range of 241-298 GHz. The port isolation was lower than - 10 dB in the frequency range of 250-298 GHz.

H. S. Black in 1928 described the principle of negative feedback using two functions denoted as A(s) and β(s). While negative feedback has many important practical benefits, circuits that utilize this principle can go unstable. In 1932 H. Nyquist described the conditions that maintain stable behavior based on the complex behavior of the product of A(s) times β(s) culminating into what is referred to as the Nyquist Stability Criterion. When applied to electronic circuits, however, there is uncertainty in identifying A(s) and β(s) due to circuit loading effects. In this paper, a theory of stability will be introduced that takes into account the influence that input and output circuit loading effects have on the operation of the circuit. An example will be used to illustrate the significance of these findings.

Graph and sparse matrix systems are highly tuned, able to run complex graph analytics in fractions of seconds on billion-edge graphs. For both developers and researchers, the focus has been on computational kernels and not end-to-end runtime. Despite the significant improvements that modern hardware and operating systems have made towards input and output, these can still become application bottlenecks. Unfortunately, on high-performance shared-memory graph systems running billion-scale graphs, reading the graph from file systems easily takes over 2000× longer than running the computational kernel. This slowdown causes both a disconnect for end users and a loss of productivity for researchers and developers.We close the gap by providing a simple to use, small, header-only, and dependency-free C++11 library that brings I/O improvements to graph and matrix systems. Using our library, we improve the end-to-end performance for state-of-the-art systems significantly—in many cases by over 40×.

This letter deals with the input-output admissibility analysis of the continuous descriptor system with a time-varying delay. A two-term approximation transformation-model has been used to convert the original system into two interconnected subsystems. Based on the scaled small gain theorem and a new Lyapunov-Krasovskii functional, a delay-dependent sufficient condition has been presented to ensure that the time-varying delay descriptor system is input-output stable, regular, and impulse free. The derived conditions are given in a set of linear matrix inequalities. Finally, an example has been used to test the merit and validity of the proposed method.

The well-known controller architecture based on the Youla parameterization is revisited in this paper. The key result in this paper is a reformulation of the Youla controller such that an exact implementation of the Youla parameterization part can be done using only terminals of the nominal controller. Further, the parameterization part does not use the nominal feedback controller directly.

Wind farms are high order systems whose dynamics are governed by non linear partial differential equations with no known analytic solution, making the design and implementation of numerical optimal controllers in high fidelity fluid dynamics solvers computationally expensive and unsuitable for real time usage. Reduced order state models provide a possible route to the design and implementation of practical cooperative wind farm controllers. This work makes use of an innovative algorithm in the context of wind farm modelling - Input Output Dynamic Mode Decomposition - to find suitable reduced order models to be used for model predictive control. The contribution of the work in this article resides in deriving a reduced order model from high fidelity simulation data where wake redirection control by yaw misalignment is evaluated. A model based predictive controller is designed and tested. In the present case study it is shown that a reduced order linear state space model with 37 states can accurately reproduce the downstream turbine generator power dynamics with a fit of 88%, reconstruct the upstream turbine wake with an average normalized root mean squared error of 4% and that optimal controllers can be designed for a collective power reference tracking problem.

Double Source SOI Tunnel FET (DSS- TFET) of both n and p-type has been proposed and influence of various parameters on the efficiency of the device have been analyzed rigorously and optimized using Silvaco-Atlas. The proposed DSS-TFET has been designed in such a way that by suppressing the ambipolar current, complementary performance can be achieved. The DSS-TFET has almost equivalent SS for different channel lengths. Hence, during circuit designing, 13nm n- type TFET and 5nm p-type TFET can be utilized which results in chip area reduction. As SOI architecture is used, ambipolar conduction has been improved, results in higher ION/IOFF ratio of. value 1013 and 1012 for both n and p type respectively.

Nowadays, hardware-based AES faces more than one type of Side-Channel-Attacks (SCA), such as the Differential Power Analysis (DPA) attack and the Differential Fault Analysis (DFA) attack. However, most of the current DFA-resistant implementations of AES only focus on resisting the DFA attack but with minimal concurrent considerations on their DPA resistance capability. In this paper, we propose a fault resistant AES with DPA awareness. First, we evaluate the DPA resistance for different implementation architectures of AES before the implementation with S-Box over GF(24)2 is selected. Second, we evaluate the DPA resistance for different fault detection architectures before the concurrent fault detection method is selected. Third, we propose a novel fault resistant technique for AES using input-output differential tables over GF(24)2. We have performed tests based on Partial Guessing Entropy (PGE) to evaluate the DPA resistance for the existing DFA-resistant designs and our proposed design. Experimental results prove that our design has a slower convergence speed (around 33%) with a 100% fault coverage rate and less area than the existing countermeasure designs for fault injection. Results also show that the fault detection designs weaken their DPA resistance, which indicates the importance of co-design of DFA and DPA to achieve less power information leakage.

In recent years, the construction and innovation of distribution network have been accelerating, and the overall investment in distribution network has been increasing year by year. Therefore, the investment efficiency of distribution network has become a key concern. At present, the evaluation system of distribution network often focuses on the technical aspects such as planning effect, safety and reliability, while lacks the evaluation of investment efficiency. In terms of investment decision, it usually makes a simple proportional allocation according to historical data. To solve the problems of the investment decision in distribution network construction, this paper puts forward an multi-factorial investment decision model, which is guided by the investment efficiency evaluation while satisfying the demand of distribution network. Firstly, the index system of input-output assessment, scoring function and investment benefit score evaluation model of regional distribution network are proposed. Secondly, the investment decision-making model based on genetic algorithm is proposed, which coordinate the balance between economy and safety of distribution network. Finally, a regional distribution network is taken as an example to test and verify the scientific usefulness of the model. The practical application results show that the multi-factorial investment decision model can promote the development and improvement of the distribution network more reasonably and economical efficiently.

Virtualization technology is the core technology of cloud computing. While virtualization technology offers flexibility in many ways, it also introduces additional performance overhead. For network systems, it needs to provide additional virtual switching, the virtual packet I/O, and other functions. Providing these features requires a lot of CPU resources. As cloud services grow, more and more CPU resources are being used to provide virtualization support, which means that fewer CPUs can be sold to tenants. Therefore, cloud service providers have been constantly seeking more efficient virtualization solutions for network systems. In this paper, we identify one of the main reasons for the large consumption of CPU resources in the virtual networking system - copy and propose to use memory page remapping technology to eliminate the copy. Moreover, to adapt to the zero-copy technology, we have integrated the technology with a mature virtual switch software in the host and a userspace protocol stack in the virtual machine. These components together build a more efficient network system in virtual environments. The evaluations with microbenchmarks and macrobenchmark show that our system performs much better than the state-of-the-art solutions.

In this paper, the measurement data loss is considered and two data-driven stochastic optimal iterative learning control (DDSOILC) methods are presented directly for nonlinear network systems. Specifically, an iterative dynamic linearization (IDL) is adopted to construct the linear incremental input output relationship of the repetitive nonlinear network system between two consecutive iterations. In the sequel, a lifted IDL is obtained by defining two super vectors of inputs and outputs over the entire finite time interval. Then, a lifted IDL-based DDSOILC scheme is proposed where the random data loss is described by a Bernoulli distribution of random variable. The results are extended by using a non-lifted IDL where the input-output relationship is described pointwisely. The learning gains of the proposed two methods are iteration-time-variant and can be iteratively estimated using real-time data. The proposed two methods do not depend on any explicit model. Moreover, the proposed non-lifted IDL-based DDSOILC can use more control information than the proposed lifted IDL-based one, and thus it can achieve a better control performance. Both theoretical analysis and simulations verify the efficiency and applicability of the two proposed methods.

Facility layout problem is one of the most important problems in a huge range of industries and services organizations. Simultaneous study of some qualitative and quantitative parameters like closeness relationship between facilities, physical constraints such as input/output points and how to arrange facilities can play a key role to determine the facility layout. Considering these parameters can lead to reduce production costs, increase production capacity, and remove additional displacements. A two-stage approach is proposed to achieve these goals. In the first stage, a goal programming model is proposed to determine weights of the attributes based on the experts' opinions with different preference representation structures. Afterwards, the closeness ratings of the facilities are calculated using weights of attributes. In the second stage, an efficient layout is designed by determining facilities placement sequence, location of the next facility adjacent to the previous one, location of input/output points, and rectilinear feasible shortest path between facilities. Two meta-heuristic algorithms including particle swarm optimization and genetic algorithm are designed due to computational complexity. The objective function is to minimize the sum of products distance between facilities and closeness rating and also to minimize the dead space. A case study of an Auto Body Parts company is demonstrated to verify the efficiency of the proposed two-stage approach. Furthermore, in order to assess the performance of the proposed approach, a comparison is drawn between the proposed approach and five existing approaches in the literature to solve different problems by using the two meta-heuristic algorithms.

Machine Hazard Risk is possible and becomes dangerous if the failure affects humans. To create a fail-safe system, industry practice is either adding redundancy in the platform or embedding a safety sensing entity inside a System on Chip (SoC). Different systems require Safety Integrity Level (SIL) certification that varies across different domains. This paper describes a systematic methodology to designing SIL compliant appliances that use SoC without safety entity paired with safety micro-controller as a platform solution. Important system level considerations and learning range from Basic Input Output System (BIOS) enhancement to platform level connectivity choices to monitors are identified and failure prediction is covered in the paper. Conference participants will learn about the methodology through a proof of concept done on a Core platform and Arduino micro-controller.

On the basis of asset classification of asset group, the specific category of asset input-output value collection of asset group of the Power Grid Company is determined. This paper systematically combs the company's intangible assets value evaluation method, intangible assets method and intangible assets classification. Starting from three aspects of security, reliability and economy of power grid operation, as well as the asset status and DEA method provided by various management departments of power grid, the input-output evaluation index system of asset group of The Power Grid Company is constructed.

This paper introduces a programmable I/O buffer that supports multiple differential standards. It is integrated in a 28nm process FPGA to implement the communication between the FPGA core and external circuits. Under different standards, its data transmission rate can reach 1.25Gbps. In the article, the design idea of important circuit modules that work with I/O buffer, such as single-ended to differential-ended module, and bias signal generation module are also introduced. On the other hand, because all circuit designs use 1.8V devices and the supply voltage of the supported differential standard is higher than 1.8V, it also has a voltage withstand function under 2.5V power supply. After the circuit design is completed, the layout is drawn. According to the simulation results, its function is correct and the transmission rate can reach the design value.

Power supply noise budget is scaled for High speed I/O Interfaces like PCIE-Gen5/6. The specification for power supply noise has become tighter and even variation of few mV is considered crucial for high speed I/O interfaces. Presently a 2.5D extraction tool is used for modelling Power delivery network interconnects for Package/Mother board. With data rates increasing, 2.5D tool lacks accuracy & there is a definite need for 3D modelling for improving the quality of the output to meet the ever-growing High speed I/Os (input output). Relying on 2.5D models can lead to pessimistic decoupling solution. The work in this paper mainly focuses on accurate interconnect modelling of Package/Motherboard using a 3-D field solver tool & also provides the impact on HSIO power supply noise and summarizes the need for this methodology upgrade. Also, paper discusses on how 3D PDN models helps design resources (SOC, PKG, BRD) to be optimized only to the most sensitive areas, thereby reducing the overall PDN resource cost.

Oak Ridge National Laboratory (ORNL) experimental neutron science facilities produce 1.2\,TB a day of raw event-based data that is stored using the standard metadata-rich NeXus schema built on top of the HDF5 file format. Performance of several data reduction workflows is largely determined by the amount of time spent on the loading and processing algorithms in Mantid, an open-source data analysis framework used across several neutron sciences facilities around the world. The present work introduces new data management algorithms to address identified input output (I/O) bottlenecks on Mantid. First, we introduce an in-memory binary-tree metadata index that resemble NeXus data access patterns to provide a scalable search and extraction mechanism. Second, data encapsulation in Mantid algorithms is optimally redesigned to reduce the total compute and memory runtime footprint associated with metadata I/O reconstruction tasks. Results from this work show speed ups in wall-clock time on ORNL data reduction workflows, ranging from 11\% to 30\% depending on the complexity of the targeted instrument-specific data. Nevertheless, we highlight the need for more research to address reduction challenges as experimental data volumes increase., Comment: 7 pages, 4 figures, International Workshop on Big Data Reduction held with 2020 IEEE International Conference on Big Data

A bidirectional three-phase high-gain converter has advantages of low current and voltage stresses, capacitor voltage self-stabilizing, inductor current self-sharing and high-gain abilities, while it also has disadvantages of narrow duty cycle range and narrow input/output voltage range, which makes the converter just suitable for high-gain applications but not wide input/output applications. A piecewise combined switching scheme is proposed, which consists of three switching strategies and can widen working duty cycle range and input/output voltage range of the converter without increasing switching voltage stress, thus makes the converter suitable for wide-input/output applications such as photovoltaic power generation, energy storage systems, DC motor control and so on. In order to analyse the effect of parasitic parameters on voltage ratio and facilitate closed-loop design of the converter, model of each strategies in Buck operation are studied. Stable-state analysis, voltage gain and switching voltage stress are also studied. Wide input/output voltage range and corresponding working duty cycle range, voltage gain and low switching voltage stress feature are verified by simulation and experiment.

The paper presents the results of calculations of the output microwave systems of broadband gyro-TWTs of the 3 mm wavelength range united in the common cascade. To achieve a high output power (300 kW), it is proposed to use a cascade of two gyro-TWTs, the first of which has a relatively high gain (40–60 dB), and the second has a high output power with a moderate gain (15–20 dB). The radiation output of the first stage is performed along the axis of the tube through the waveguide depressed collector. The microwave system of the second stage has a transverse radiation input-output through a single barrier window with the signal separation by their polarizations. The transformation of wave fields is carried out by waveguide converters and a system of external quasi-optical mirrors. The calculated efficiency of the output system in the frequency range 90–100 GHz exceeds 95%. The paper compares the methods and approaches used to model the microwave systems.

The low-frequency noise of input-output (I/O) FinFETs with 3.5 nm and 5nm SiO 2 gate dielectric is studied for different processing conditions. For the thin dielectric a high-pressure (HP) deuterium anneal can improve the noise Power Spectral Density (PSD). There is no significant impact on n-channel devices, while a pronounced effect is observed for p-channel devices, especially for a HP anneal at 400 °C and 20 atm. Results are also presented on the use of a Si/SiGe superlattice architecture and it is shown that the same gate stack quality as for standard devices can be maintained.

As high-performance computing (HPC) is being scaled up to exascale to accommodate new modeling and simulation needs, I/O has continued to be a major bottleneck in the end-to-end scientific processes. Nevertheless, prior work in this area mostly aimed to maximize the average performance, and there has been a lack of study and solutions that can manage I/O performance variation on HPC systems. This work aims to take advantage of the storage characteristics and explore application level solutions that are interference-aware. In particular, we monitor the performance of data analytics and estimate the state of shared storage resources using discrete fourier transform (DFT). If heavy I/O interference is predicted to occur at a given timestep, data analytics can dynamically adapt to the environment by lowering the accuracy and performing partial or no augmentation from the shared storage, dictated by an augmentation-bandwidth plot. We evaluate three data analytics, XGC, GenASiS, and Jet, on Chameleon, and quantitatively demonstrate that both the average and variation of I/O performance can be vastly improved using our dynamic augmentation, with the mean and variance improved by as much as 67% and 96%, respectively, while maintaining acceptable outcome of data analysis.

Feedback linearization utilizes an efficient linearizing control to make the input-output nonlinear dynamics of a plant linear such that multiple linear control methods can be used to track output trajectories to the desired one. The open problems in control of feedback linearizable systems are the identification of dynamics in terms of coefficients and system states. Therefore, the input-output linearization based control with LMI based state observer is presented for a DC-DC buck converter in CCM(Continuous Conduction Mode) mode. The LMI approach for observer ensures robustness to additive and environmental system uncertainties. However, the exact knowledge of system parameters is obligatory during closed-loop system operation.Parameter estimation is performed in open loop using DREM(Dynamic Regression Extension and Mixing) technique to improve transient response and finite time parameter convergence. The feedback control law, state and parameter estimations are simulated on MATLAB/SIMULINK.

With the growing complexity of high-performance computing (HPC) systems, achieving high performance can be difficult because of I/O bottlenecks. We analyze multiple years’ worth of Darshan logs from the Argonne Leadership Computing Facility’s Theta supercomputer in order to understand causes of poor I/O throughput. We present Gauge: a data-driven diagnostic tool for exploring the latent space of supercomputing job features, understanding behaviors of clusters of jobs, and interpreting I/O bottlenecks. We find groups of jobs that at first sight are highly heterogeneous but share certain behaviors, and analyze these groups instead of individual jobs, allowing us to reduce the workload of domain experts and automate I/O performance analysis. We conduct a case study where a system owner using Gauge was able to arrive at several clusters that do not conform to conventional I/O behaviors, as well as find several potential improvements, both on the application level and the system level.

As modern parallel computers enter the exascale era, the communication cost for redistributing requests becomes a significant bottleneck in MPIIO routines. The communication kernel for request redistribution, which has an all-to-many personalized communication pattern for application programs with a large number of noncontiguous requests, plays an essential role in the overall performance. This paper explores the available communication kernels for two-phase I/O communication. We generalize the spread-out algorithm to adapt to the all-to-many communication pattern of two-phase I/O by reducing the communication straggler effect. Communication throttling methods that reduce communication contention for asynchronous MPI implementation are adopted to improve communication performance further. Experimental results are presented using different communication kernels running on Cray XC40 Cori and IBM AC922 Summit supercomputers with different I/O patterns. Our study shows that adjusting communication kernel algorithms for different I/O patterns can improve the end-to-end performance up to 10 times compared with default MPI-IO implementations.

Improvements in I/O architectures are becoming increasingly required nowadays. This is an essential point to complex and data intensive scalable applications. Data-Intensive Scalable Computing (DISC) and High-Performance Computing (HPC) applications frequently need to transfer data between storage resources. In the scientific and industrial fields, the storage component is a key element, because usually those applications employ a huge amount of data. Therefore, the performance of these applications commonly depends on some factors related to time spent in execution of the I/O operations. However, researchers, through their works, are proposing different approaches targeting improvements on the storage layer, thus, reducing the gap between processing and storage. Some solutions combine different hardware technologies to achieve high performance, while others develop solutions on the software layer. This paper aims to present a characterization model for classifying research works on I/O performance improvements for large scale computing facilities. Analysis over 36 different scenarios using a synthetic I/O benchmark demonstrates how the latency parameter behaves when performing different I/O operations using distinct storage technologies and approaches.

Input/Output (I/O) automata are widely used when deriving high quality tests for (components of) complex discrete systems based on so called distinguishing sequences. For I/O automata, the number of distinguishability relations is much bigger than for classical deterministic Finite State Machines (FSM). In order to avoid submitting the same test sequence several number of times, i.e., avoid the "all weather conditions" assumption, the separability relation can be considered. If two Input/Output automata are separable then there exists an input sequence such that after submitting this sequence and observing produced outputs it can be uniquely concluded which automaton is under testing. In this paper, we modify the discipline of applying input sequences and discuss the derivation of separating sequences for automata with mixed states, i.e., states where transitions both under inputs and under outputs are defined, as well as with cycles labeled by outputs. We also illustrate how an adaptive separating sequence can be derived when both automata are input-enabled.

Sensor data can be used to diagnose the system's health. A challenge comes when the data contain missing or invalid data. It is common that sensors misread for various reasons. So, data contain missing measurements and sensor saturation. The main contribution in this paper is to implement a method based on the Input-Output Hidden Markov Model that trains the model using the missing measurements and sensor saturation, then diagnoses the system health at given operating conditions. Usually, if a data set contains some sequences with missing elements then they can be excluded from the analysis. It cleans the data set but reduces its size. This strategy knows as list-wise or case-wise deletion is less suitable for real application cases. The proposed method includes the sequences with missing data into the analysis by generating the missing elements to complete the sequence. The maximum likelihood is applied to estimate IOHMM parameters that offer substantial improvements over list-wise deletion. A numerical application with simulated data sets illustrates the method.

We present a 40-nm multi-scale object detection processor with only three operations: $3\times 3$ convolution, $1\times 1$ convolution, and $4\times 4$ deconvolution. The multi-scale object detection at high accuracy is possible by virtue of the deconvolution feature. Input memory for a feature map has 8-bit width as well as a multiplier for the inputs has 8-bit precision. Partial-sum memory, however, has 16-bit width to suppress detection accuracy deterioration in a layer with 512 channels or more. By fixed-point bit precision, the external memory bandwidth and internal memory capacity are reduced. optimized parallelization in input and output channels reduces the external memory bandwidth to 0.50 GB per $1280\times 384$ image with internal memory capacity of 400 kB. The detection error is 1.9% of that using single-precision floating point. The maximum operating frequency is 500 MHz at a supply voltage of 1 V. Its peak performance is 1.15 TOPS. The maximum energy efficiency is 6.57 TOPS/W at 174 MHz and 0.6 V.

In this paper, the input and output couplers are designed and simulated for a frequency range of 14.9 to 15.4 GHz Ku-band over 1 kW power. The input coaxial coupler section comprises of an impedance transition with the coaxial ceramic window of 99.5% alumina to handle the maximal input power less than 1 watt. In the output coupler, coaxial to waveguide (WR-62) progression is used to handle the maximal power from the TWT. Initially, the couplers are designed theoretically. Further, the designs are optimized by commercially available 3-D electromagnetic simulation software, micro-wave studio (MWS), computer simulation technology (CST). The Eigen mode simulations for both the couplers give the voltage standing wave ratio (VSWR) value of less than 1.20.

Based on practical problems, such as power transmission and internet of things, this paper establishes a class of discrete switched networked control model. For the model, we propose input-output finite-time stability (I-O FTS) definition. Furthermore, we formulate the corresponding stability theorem, and then, transform this theorem into conditions with matrix constraints. To conclusion this paper, we use these conclusions to solve I-O FTS problem for a kind of power transmission systems.

Bioinformatics software often integrates multiple off-the-shelf programs into a single compute pipeline. Each stand-alone program generates output, that is frequently saved into a plain-text file, which is then processed as input by the program that is responsible for the next stage of the computation. Modern advances in genome sequencing and protein structure resolution methods have yielded large amounts of data, that when processed by bioinformatics compute pipelines, results in vast numbers of file reads and writes. Since computation capabilities of large-scale distributed systems grow much faster than their I/O bandwidth, processing such big data using these compute pipelines will not scale as the amount of data grows. For this work, we motivate and demonstrate a dynamic interception-based I/O analysis tool to assess the file read and write characteristics of a protein mutation generation pipeline. We discuss how our analysis tool can be further extended to apply compression and in-site analysis and has the potential to scale I/O-intensive bioinformatics applications on high performance computing (HPC) systems.

IONMP-[4] Stands for Input Output Nodes Messaging Protocol. It is a plug and play - [20] protocol that allows sensors and actuators to register with an infrastructure, and advertise their identity / capabilities. It also provides a standard way for sensors to publish their readings and actuators to be controlled by the infrastructure. Thanks to the plug and play protocol, the participants of the system do not need to know about the capabilities of other entities at deploy time. This protocol allows entities to query about the capabilities of other participants at run time to define event action relationships.

Every day, the power system receives massive I/O logs. The amount of data in these logs is so large that it takes huge computational resources to analyze. Therefore, it is necessary to reduce the size of the massive I/O logs and only analyze the key log data, thereby reducing the workload of invalid analysis. This paper takes the I/O log of the substation as the research object, and studies the dimension reduction method of the massive I/O data flow log, which reduces the computational load brought by the high-dimensional I/O data flow log data and reduces the massive I/O data flow log. This paper proposes a method of secondary dimensionality reduction. Firstly, the high dimensional I/O log data stream is classified, so that the data is transformed from high-dimensional to low-dimensional. Then, the dimension is reduced again in each category, so that the most simplified massive I/O logs are achieved. Through theoretical analysis, we can come to the conclusion that the computational time complexity of the data after dimension reduction is reduced by more than 80%.

This paper studies the input/output-to-state stability (IOSS) and integral IOSS (iIOSS) of nonlinear systems with delayed impulses. In order to address flexible delays in impulses, the method of average impulsive delay (AID) is used to describe such impulses, and it is said to be the average-delay impulses. Further, by using the method of average impulsive interval (AII), we propose some criteria for IOSS and iIOSS of the system with average-delay impulses. To be specific, a uniform relationship is established among the AII and AID constants, impulses, and the decay rate of the continuous dynamics such that IOSS and iIOSS of the system with average-delay impulses are guaranteed, respectively. Some illustrative examples are presented to show the validity of the obtained results.

General-purpose I/O widely exists on multi- and many-core systems. For real-time applications, I/O operations are often required to be timing-predictable, i.e., bounded in the worst case, and timing-accurate, i.e., occur at (or near) an exact desired time instant. Unfortunately, both timing requirements of I/O operations are hard to achieve from the system level, especially for many-core architectures, due to various latency and contention factors presented in the path of instigating an I/O request. This paper considers a dedicated I/O co-processing unit, and proposes two scheduling methods, with the necessary hardware support implemented. It is the first work that guarantees timing predictability and maximises timing accuracy of I/O tasks in the multi-and many-core systems.

Robust stabilization problem for a linear multivariable system with parametric uncertainty is considered. In addition it is required to provide stability margins at the physical input/output of a control plant. Solution of the problem is based on a H ∞ optimization formulated in the special way. Numerical solution of such a problem uses linear matrix inequalities (LMI) technique developed in the well-known MATLAB-package Robust Control Toolbox. Illustrative example of the considered problem solution is presented.

The input-output table reflects the interaction and dependence between industrial sectors, and the flow of products reflects the influence of each sector in the national economy. In this paper, the weighted PageRank algorithm in the field of complex networks is used to rank the importance of each sector in the input-output table of China's 42 × 42 in 2017. The sorting results are explained based on the principle of the algorithm, which shows the effectiveness of the algorithm in identifying key departments. Among them, due to the attention and investment of the state, the three sectors including Architecture, Public management and social security, and Transportation equipment, have shown significant advantages, so they have achieved a higher position than other sectors.

This paper takes the five private express listed companies in China as the research object, adopts the principal component analysis method and establishes the DEA-Malmquist index model to establish a comprehensive input-output index system, and measures the input-output efficiency of these five companies from 2017 to 2019. The results show that in the past three years, the input-output efficiency of these five companies have grown rapidly. However, there are problems of weak technical level, inconsistent production scale and R & D investment level. Finally, put forward relevant suggestions to help express companies optimize their structure and improve logistics efficiency.

An energy efficient Deep-Neural-Network (DNN) learning processor is proposed for on-chip learning and iterative weight pruning (WP). This work has three key features: 1) stochastic coarse-fine pruning reduced computation workload by 99.7% compared with previous WP algorithm while maintaining high weight sparsity, 2) adaptive input/output/weight skipping (AIOWS) achieved 30.1× higher throughput than previous DNN learning processor [1] for not only the inference but also learning, 3) weight memory shared pruning unit removed on-chip weight memory access for WP. As a result, this work shows 146.52 TOPS/W energy efficiency, which is 5.79× higher than the state-of-the-art [1].