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We have already proposed the inverse function delayed (ID) model as a novel neuron model. The ID model has negative resistance similar to Bonhoeffer-van der Pol (BVP) model and the network has an energy function similar to Hopfield model. The neural network having an energy can converge on a solution of the combinatorial optimization problem and the computation in parallel and hence fast. However, the existence of local minima is a serious problem. The negative resistance of the ID model can make the network state free from such local minima by selective destabilization. Hence, we expect that it has a potential to overcome the local minimum problems. In computer simulations, we have already Shown that the ID network can be free from local minima and that it converges on the optimal solutions. However, the theoretical analysis has not been presented yet. In this paper, we redefine three types of constraints for the particular problems, then analytically estimate the appropriate network parameters giving the global minimum states only. Moreover, we demonstrate the validity of estimated network parameters by computer simulations. [ABSTRACT FROM AUTHOR]

We propose a neuron-synapse integrated circuit (IC) chip-set for large-scale chaotic neural networks. We use switched-capacitor (SC) circuit techniques to implement a three-internal-state transiently-chaotic neural network model. The SC chaotic neuron chip faithfully reproduces complex chaotic dynamics in real1numbers through continuous state variables of the analog circuitry. We can digitally control most of the model parameters by means of programmable capacitive arrays embedded in the SC chaotic neuron chip. Since the output of the neuron is transfered into a digital pulse according to the all-or-nothing property of an axon, we design a synapse chip with digital circuits. We propose a memory-based synapse circuit architecture to achieve a rapid calculation of a vast number of weighted summations. Both of the SC neuron and the digital synapse circuits have been fabricated as IC forms. We have tested these IC chips extensively, and confirmed the functions and performance of the chip-set. The proposed neuron-synapse IC chip-set makes it possible to construct a scalable and reconfigurable large-scale chaotic neural network with 10000 neurons and 100002 synaptic connections. [ABSTRACT FROM AUTHOR]