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In this work, we have analyzed novel p-channel nanosheet-FET (NSFET) architectures, which utilize Ge channel grown heteroepitaxially on GaAs with an intermediate AlAs etchstop/ buffer layer. The lattice matched Ge/AlAs heterostructure offers significant benefits for gate all-around (GAA) CMOS devices such as: (i) defect-free interface and channel, (ii) ease of fabrication owing to ~ 105:1 etch selectivity between AlAs and Ge, (iii) well-established and transferrable material growth and process, (iv) superior performance and low-power dissipation, (v) no limitation of sheet thickness, and (vi) higher number of vertically stacked sheets. The transition from the well-established FinFET architecture to the Ge p-NSFET will improve ION by 12% to 0.11 mA/μm, SS by 9% to 86 mV/dec and ION/IOFF ratio by ~ 5×, at the N5 node. In addition, the use of InxGa1-xAs strain template to sustain a tunable tensile strain in Ge through pseudomorphic growth, can result in an additional 40% improvement in ION and 8% in SS, at a strain of 1% for the p-NSFET. Leveraging the lattice matched Ge/AlAs growth, the 3D stacking of a large number of nanosheets is possible, and a significant boost in ION (~ 4×) is obtained with 8 layers despite of parasitics induced selfloading. In applications requiring high drive current, increasing the number of stacked Ge nanosheets is the most efficient design pathway to improve circuit delay and area-delay-product. This system shows suitability for low-power and high-performance applications for dimensions down to N0.7, where the ION is ~ 0.6mA/μm and the SS is 81 mV/dec. Accepted version

In this work, we have studied the effect of material parameters (indium (In) composition and doping), geometrical parameters (channel length L, fin width W, aspect ratio AR), and quantum confinement (QC) on the performance and operability of a ε-Ge/InxGa1-xAs hybrid CMOS system. In this system, the In compositional InxGa1-xAs and tensile strained Ge (ε-Ge) grown on the InxGa1-xAs layer, were used as n- and p-channel FinFETs, respectively. The In composition in InxGa1-xAs layer (lattice matched with graded InxAl1-xAs buffer) determines the amount of tensile strain in Ge. This hybrid system utilizes the benefits of metamorphic (InxGa1-xAs/InxAl1-xAs) as well as pseudomorphic (ε- Ge/InxGa1-xAs) heteroepitaxy to create high performance tunable complementary devices, suitable for 0.5 V CMOS operation. The device metrics such as, threshold voltage, on-current (ION), offcurrent (IOFF), subthreshold-swing (SS), and drain induced barrier lowering (DIBL), and their dependence on material and geometrical parameters were evaluated using self-consistent analytical solvers scaled down to the N5 node. At these scaled dimensions, this hybrid system demonstrated ultra-low leakage current and SS for the n-FinFET and p-FinFET of 10 pA/μm, 27 nA/μm, 85 mV/dec and 95 mV/dec, respectively. With the effect of QC, we identify a transition fin width (WT) associated with scaling of alternate channel FinFETs, at which the performance is optimum and below WT, the benefits of scaling are diminished. Moreover, this hybrid system has a potential to find applications in optoelectronic and RF systems as well as high-performance computing. Accepted version

The lack of reports on the high-temperature performance of tri-gate GaN power HEMTs has raised serious concern on their competitiveness. This work demonstrates the first normally-off tri-gate GaN HEMT that can block kilovolts at 150 °C and zero gate bias. The key enabling device design is a new type of tri-gate, the junction tri-gate, which comprises p-n junction wrapping around AlGaN/GaN fins in the gate region. At 150 °C, the GaN tri-gate junction HEMT (Tri-JHEMT) retains strong gate control and stable threshold voltage, while the traditional tri-gate metal-insulator-semiconductor (MIS) HEMTs fabricated on the same wafer shows a large threshold voltage shift and inferior capabilities of voltage blocking. These results show the excellent thermal stability of GaN Tri-JHEMTs and their great potentials for power electronics applications.

A novel, tunnel field-effect transistor (TFET)-based adiabatic logic (TBAL) circuit topology has been proposed, evaluated and benchmarked with several device architectures (planar MOSFET, FinFET, and TFET) and AL implementations (efficient charge recovery logic, 2N-2N2P, positive feedback adiabatic logic) operating in the ultra-low voltage (0.3 V ≥ VDD ≤ 0.6 V) regime. By incorporating adiabatic logic functionality into standard combinational logic, an 80% reduction in energy/cycle was achieved. A further 80% reduction in energy/cycle was demonstrated by utilizing near broken-gap TFET devices and simultaneous scaling of supply voltage to 0.3 V, resulting in a 96% reduction in energy/cycle as compared to conventional Si CMOS. Extension of operating frequency beyond 10 MHz, coupled with sub-threshold circuit operation, shows the feasibility of TBAL for energy-efficient Internet of Things applications.

Structural and electrical characteristics of epitaxial germanium (Ge) heterogeneously integrated on silicon (Si) via a composite, large bandgap AlAs/GaAs buffer are investigated. Electrical characteristics of N-type metal-oxide-semiconductor (MOS) capacitors, fabricated from the aforementioned material stack are then presented. Simulated and experimental X-ray rocking curves show distinct Ge, AlAs, and GaAs epilayer peaks. Moreover, secondary ion mass spectrometry, energy dispersive X-ray spectroscopy (EDS) profile, and EDS line profile suggest limited interdiffusion of the underlying buffer into the Ge layer, which is further indicative of the successful growth of device-quality epitaxial Ge layer. The Ge MOS capacitor devices demonstrated low frequency dispersion of 1.80% per decade, low frequency-dependent flat-band voltage, $V_{FB}$ , shift of 153 mV, efficient Fermi level movement, and limited C-V stretch out. Low interface state density $(D_{it} )$ from $8.55 \times 10^{11} $ to $1.09 \times 10^{12}~ {\rm cm}^{-2} ~{\rm eV}^{-1} $ is indicative of a high-quality oxide/Ge heterointerface, an effective electrical passivation of the Ge surface, and a Ge epitaxy with minimal defects. These superior electrical and material characteristics suggest the feasibility of utilizing large bandgap III-V buffers in the heterointegration of high-mobility channel materials on Si for future high-speed complementary metal-oxide semiconductor logic applications.

In this paper, for the first time, the performance analysis of short channel In₀.₅₃Ga₀.₄₇As quantum well (QW) 3-D tri-gate technology with advanced high-κ gate dielectric, TaSiOx is presented. We benchmark the projected performance of sub-10 nm In₀.₅₃Ga₀.₄₇As transistor technology as a function of fin width, fin aspect ratio, and gate length scaling based on present-day lithographic advancement aiding InGaAs QW tri-gate technology as a replacement to Si for sub-10 nm transistor technology. The highly scaled oxide (EOT ∼ 12Å) while retaining superior interfacial properties (Dit ∼ 4 × 10¹¹ cm⁻²eV⁻¹) provides higher ON current for given idle performance. Furthermore, the simulated In₀.₅₃Ga₀.₄₇As tri-gate transistor exhibits superior gate electrostatic control with low OFF-state current (IOFF) ∼ 24.5 nA/μm, peak transconductance (gm) ∼ 2 mS/ μm and high ION/IOFF ratio ∼ 2.3 × 10³, aiding the case of alternate channel transistors for high-speed and low-power CMOS logic.

We have demonstrated the impact of buffer architectures on the performance of 1J GaAs solar cells heterogeneously integrated on Si. An all-epitaxial molecular beam epitaxy-grown thin (

The human face plays a prodigious role for automatic recognition of emotion in the field of identification of human emotion and the interaction between human and computer for some real application like driver state surveillance, personalized learning, health monitoring etc. Most reported facial emotion recognition systems, however, are not fully considered subject-independent dynamic features, so they are not robust enough for real life recognition tasks with subject (human face) variation, head movement and illumination change. In this article we have tried to design an automated framework for emotion detection using facial expression. For human-computer interaction facial expression makes a platform for non-verbal communication. The emotions are effectively changeable happenings that are evoked as a result of impelling force. So in real life application, detection of emotion is very challenging task. Facial expression recognition system requires to overcome the human face having multiple variability such as color, orientation, expression, posture and texture so on. In our framework we have taken frame from live streaming and processed it using Grabor feature extraction and neural network. To detect the emotion facial attributes extraction by principal component analysis is used and a clusterization of different facial expression with respective emotions. Finally to determine facial expressions separately, the processed feature vector is channeled through the already learned pattern classifiers.

Integration of III–V multijunction solar cells on Si substrate can address the future levelized cost of energy by unifying the high-efficiency merits of III–V materials with the low-cost and abundance of Si. A Si-compatible monolithically integrated 3J InGaP/GaAs/Ge-Si cell design with a hybrid Ge-Si bottom cell is investigated. Utilizing a combination of comprehensive modeling and experimental material characterization techniques, we present our results for ultrathin epitaxial Ge directly grown on Si substrate using molecular beam epitaxy. Virtual “Ge-on-Si” substrates could provide a large-area, low-cost alternative to expensive GaAs wafers, a promising step towards realizing monolithic, high-efficiency and low-cost III–V-on-Si photovoltaics.

Integration of III–V multijunction solar cells on Si substrate is highly sought for achieving lower levelized cost of energy by unifying the high-efficiency merits of III–V materials with low-cost and abundance of Si. Triple-junction (3J) InGaP/GaAs/Si solar cells with an active Si bottom cell are investigated for concentrated photovoltaic (CPV) operation under AM1.5d spectrum. We present key insight into the design of GaAs buffer architecture for the optimal down-selection of the buffer doping and thickness to maximize the photon flux penetration to the bottom Si subcell. Ideal case scenario employing dislocations free III–V solar cells directly integrated onto the Si subcell without a buffer layer yielded current-matched 1-sun 3J efficiency of 32.13% and 36.39% under AM1.5d and AM1.5g spectra, respectively. Under AM1.5d the efficiency dropped to 29.30% and 27.32% at a threading dislocation density (TDD) of 106 cm−2 and 107 cm−2, respectively, when 0.5 µm thick GaAs buffer was employed between the III–V subcells and the bottom Si subcell. Finally, we present a novel design for heterogeneously integrated 3J InGaP/GaAs/Si tandem solar cell incorporating a TDD of 106 cm−2 with an efficiency exceeding 33% at 200 suns, indicating a promising future for III–V on Si photovoltaics for CPV operation.

Staggered tunnel junction (GaAs 0.35 Sb 0.65 /In 0.7 Ga 0.3 As) is used to demonstrate heterojunction tunnel FET (TFET) with the highest drive current, I on , of 135µA/µm and highest I on /I off ratio of 2.7×104 (V ds =0.5V, V on −V off =1.5V). Effective oxide thickness (EOT) scaling (using Al 2 O 3 /HfO 2 bilayer gate stack) coupled with pulsed I–V measurements (suppressing D it response) enable demonstration of steeper switching TFET.

Heterogeneous integration of multijunction III–V solar cells on Si is a promising solution for the widespread commercialization of III–V cells. However, the polar on non-polar epitaxy and 4% lattice-mismatch between GaAs and Si results in formation of defects and dislocations, which can significantly impede the minority carrier lifetime and hence the cell performance. We have investigated the impact of threading dislocation density on the performance of dual-junction (2J) n+/p InGaP/GaAs solar cells on Si. Using our calibrated model, the metamorphic 2J cell on Si was optimized by tailoring the 2J cell design on Si to achieve current-matching between the subcells at a realistic threading dislocation density of 106 cm−2. We present a novel 2J InGaP/GaAs cell design on Si at a threading dislocation density of 106 cm−2 which exhibited a theoretical conversion efficiency of greater than 29% at AM1.5G spectrum, indicating a path for viable III–V multijunction cell technology on Si.

Antimonide based compound semiconductors have gained considerable interest in recent years due to their superior electron and hole transport properties [1–3]. Among the various high mobility material systems (Fig. 1), arsenic-antimonide based MOS-HEMTs have great potential to enable complementary logic operation at low supply voltage. Integrating a high quality dielectric is key to demonstrating a scalable arsenic-antimonide MOS-HEMT architecture for 15 nm logic technology node and beyond. It is hypothesized that an ultra-thin GaSb surface layer is more favorable toward high-к integration than In 0.2 Al 0.8 Sb barrier as it avoids Al at the interface and the associated surface oxidation. Here, we study the effects of various surface passivation approaches on the capacitance-voltage characteristics (C-V) and the surface chemistry of n-type and p-type GaSb(100) MOS capacitors made with ALD and Plasma Enhanced ALD (PEALD) Al 2 O 3 dielectric. We demonstrate for the first time, unpinned Fermi level in GaSb MOS system with high-к PEALD Al 2 O 3 dielectric using admittance spectroscopy and XPS analysis.

Compound semiconductor high electron mobility transistors (HEMTs) have recently gained a lot of interest for future high-speed, low-power logic applications due to their high mobility and high effective carrier velocity [1]. Conventional In 0.7 Ga 0.3 As HEMTs with 50 to 150nm gate-length (L G ) have been experimentally demonstrated [2] with excellent device performance. In this paper, (i) we use two-dimensional numerical drift-diffusion simulations [3] to model the conventional In 0.7 Ga 0.3 As HEMTs with different L G from 15 to 200nm and investigate its scalability for future logic applications. (ii) An accurate estimation of effective mobility (μ eff ) and effective carrier velocity (injection) is presented, highlighting the relevance of ballistic mobility in these short-channel HEMTs. (iii) Due to degradation in performance of the conventional scaled In 0.7 Ga 0.3 As HEMT at L G =15nm, three novel HEMT device architectures are studied and the design for the ultimate scaled transistor is proposed.

This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO x -2nm InP) in the In 0.7 Ga 0.3 As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (t OXE ) and low gate leakage (J G ) and (ii) effective carrier confinement and high effective carrier velocity (V eff ) in the QW channel. The L G =75nm In 0.7 Ga 0.3 As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750µS/µm and high drive current of 0.49mA/µm at V DS =0.5V.

This paper describes about III-V integration on silicon and summarizes the recent progress on the research efforts to combine the merits of III-V and silicon, on the same silicon wafer, for future high-speed and low-power nanoelectronics. The successful integration of III-V on silicon can open up opportunities for integrating new functionalities and features on silicon, such as integrating logic, optoelectronic and communication platforms on the same Si wafer.

This paper describes for the first time, the heterogeneous integration of In0.7Ga0.3As quantum well device structure on Si substrate through a novel, thin composite metamorphic buffer architecture with the total composite buffer thickness successfully scaled down to 1.mum, resulting in high- performance short-channel enhancement-mode In0.7Ga0.3As QWFETs on Si substrate for future high-speed digital logic applications at low supply voltage such as 0.5 V.

In this paper we report growth, fabrication and characterization of In/sub 0.52/Al/sub 0.4/sAs/In/sub 0.53/Ga/sub 0.47/As/InAs/sub 0.3/P/sub 0.7/ composite channel HEMTs with a gate length of 0.25 /spl mu/m. In comparison with InAlAs/InGaAs/InP composite channel HEMTs, these devices have better band structure for transferring electrons to the composite channel under high electric field, thus exhibit excellent DC and microwave performance with a peak extrinsic transconductance of 888.3 mS/mm, an f/sub T/ of 115 GHz, and an f/sub max/ of 137 GHz. To our knowledge, this is the first report of InAlAs/InGaAs/InAsP composite channel HEMTs. The f/sub T/ is the highest ever reported for any composite channel HEMTs with the same gate length.

Single junction GaAs solar cells having an n/p polarity were grown on p-type Ge/SiGe/Si substrates for the first time. The cell performance and material properties of these n/p cells were compared with p/n cells grown on n-type Ge/SiGe/Si substrates for which record high minority carrier hole lifetimes of 10 ns and open circuit voltages (V/sub oc/) greater than 980 mV (AM0) were achieved. The initial n/p experimental results and correlations with theoretical predictions have indicated that for comparable threading dislocation densities (TDD), n/p cells have longer minority carrier diffusion lengths, but reduced minority carrier lifetimes for electrons in the p-type GaAs base layers. This suggests that a lower TDD tolerance exists for n/p cells compared to p/n cells, which has implications for the optimization of n/p high efficiency cell designs using alternative substrates.

The present paper describes the results from the growth of undoped epitaxial GaAs by low pressure Metal Organic Chemical Vapor Deposition (MOCVD) and its structural and electrical properties. The growth temperature and pressure were 700/spl deg/C and 100 Torr, respectively. Growth was carried out at different V/III ratios and hydrogen flow rates. Epilayers thus grown were shown to have uniform thickness, smooth surface, crystalline structure, stoichiometric and low background impurity concentration. The increasing V/III ratio resulted in the p-to n-type transformation of the epilayers. With increasing hydrogen flow rate, the background carrier concentration was decreased. Hall mobility of 90,000 cm/sup 2/ V/sup -1/ s/sup -1/ at 77 K for a carrier concentration of 1/spl times/10/sup 15/ cm/sup -3/ was obtained.

Low temperature photoluminescence spectroscopy is used extensively to study the distribution of defects, concerning the type and impurity in a semiconductor film. Typical photoluminescence spectra are observed in a near band edge region. The undoped GaAs epitaxial layers grown by low pressure metal organic vapor phase epitaxy under different V/III ratios, an optimum ratio corresponding to a minimum number of shallow impurities was clearly identified. The V/III ratio has strong effect on the optical properties of undoped GaAs epitaxial layers. When the V/III ratio was varied from 45 to 87, the electron concentration, n, of undoped GaAs increased with increasing V/III ratio. Below the V/III ratio of 45 in our case, the sample exhibited a p-type behavior, which has been identified by photoluminescence as well as depth profiling by Electro-chemical Capacitance Voltage (ECV) profiler.

Single junction AlGaAs/GaAs and InGaP/GaAs solar cells and test structures have been grown by molecular beam epitaxy (MBE) and metalorganic chemical vapor deposition (MOCVD), respectively, on Si wafers coated with compositionally-graded GeSi buffers. The combination of controlled strain relaxation within the GeSi buffer and monolayer-scale control of the Ill-V layer nucleation is shown to reproducibly generate minority carrier lifetimes exceeding 10 nanoseconds within GaAs overlayers. The III-V layers are free of long-range antiphase domain disorder, with threading dislocation densities in the high-10/sup 5/ cm/sup -2/ range, consistent with the low residual dislocation density in the Ge cap of the graded buffer structure. Single junction GaAs cells grown by both MBE and MOCVD on the Ge/GeSi/Si substrates demonstrated high V/sub oc/ values for GaAs cells grown on Si. Record V/sub oc/ values for MOCVD-grown single junction InGaP/GaAs cells exceeded 980 mV (AMO) with fill factors of 0.79. Additionally, external quantum efficiency data indicates no degradation in carrier collection from GaAs homoepitaxial cells for current single-junction cell designs grown by MBE. Based on these results, cell efficiencies in excess of 18.5% under AM0 conditions should be attainable with cell designs demonstrating state of the art J/sub sc/ values. Such cell performance demonstrates the potential and viability of graded GeSi buffers for the development of Ill-V cells on Si wafers.