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In this paper, a whole frame loss error concealment algorithm for three-dimensional video coding is proposed. The main concept of the proposed algorithm is to extrapolate the motion vectors for concealing a current error block by jointly considering the available motion vector and the depth information. In addition, the depth information is adopted to help the derivation of reference pixels for concealing errors in the case that suitable motion vectors cannot be obtained by the motion vector extrapolation process alone. Simulation results demonstrate that our proposed algorithm can achieve up to 0.52 dB PSNR, as well as subjective quality improvement, compared to previous work. [ABSTRACT FROM PUBLISHER]

A new distributed amplifier (DA) topology is proposed, which is a combination of the conventional DA and the cascaded single-stage DA. This DA topology can provide wide bandwidth with considerations of the gain, noise figure (NF), and output power simultaneously, and requires reasonable dc power consumption. In this paper, two termination methods of this combination are investigated. From the measurements, the first DA proposed by Chen in 2011 has a small-signal gain of 20.5 dB, a 3-dB bandwidth of 35 GHz, and a gain-bandwidth (GBW) product of 371 GHz. The maximum output power at 1-dB output compression point (OP1~{dB}) is 8.6 dBm and the NF is between 6.8–8 dB at frequencies lower than 18 GHz. The chip size, including testing pads, is only \ 0.78 mm^2, and the ratio of the GBW to chip size is \476 GHz/mm^2. The second DA has a small-signal gain of 24 dB, a 3-dB bandwidth of 33 GHz, and a GBW product of 523 GHz. The maximum OP1~{dB} is 9 dBm and the NF is between 6.5–7.5 dB at frequencies lower than 18 GHz. The chip size including testing pads is only \ 0.83 mm^2, and the ratio of the GBW to chip size is \630 GHz/\ mm^2. To the authors' knowledge, the second circuit has the highest ratio of GBW to chip area and the highest figure-of-merit in \0.18- \mu\ m CMOS, and it has a comparable performance with other DAs in advanced process. [ABSTRACT FROM AUTHOR]

This paper presents a 17 GHz to 35 GHz broadband power amplifier (PA) using 0.15-\mum GaAs pHEMT technology. The synthesized transformer using microstrip line matching technique is proposed in this PA design to enhance the broadband frequency response and minimize the chip size. The design procedures are also presented. A high efficiency broadband PA in commercial 0.15 \mum GaAs pHEMT process with the best P1\,dBof 22 dBm, Psat of 23.5 dBm, and PAE of 40% are demonstrated to verify the design concepts. This PA has the highest PAE, smallest chip size, and wide fractional bandwidth among the broadband GaAs HEMT PAs from K to Ka band. [ABSTRACT FROM PUBLISHER]

In this paper, an X-band pseudomorphic HEMT power amplifier (PA) is reported with two kinds of hysteresis phenomena; the first occurs in the dc–IV measurement, and the second is observed in the power measurement. The unusual phenomena can be attributed to the gate current resulting from the impact ionization coupling with the gate bias resistor, which is usually observed in the design of RF circuits to provide the gate bias. After the gate current is considered, two methods are proposed to analyze the hysteresis with the same conclusion. The cause of the encountered hysteresis is for the first time identified, and criteria for the selection of the gate bias resistor in order to avoid the hysteresis are proposed. Finally, a PA complying with these criteria is presented with good performances and without hysteresis. [ABSTRACT FROM AUTHOR]

This paper presents a wideband power amplifier (PA) for the application of intelligent cognitive radios. Resistive feedback and transformer matching network are proposed in this PA design to enhance the broadband frequency response. The broadband load impedance match is realized using series stack topology. The limitation of stack PA in both GaAs and CMOS processes are discussed. A high-efficiency broadband PA in commercial 0.18 \mum CMOS process with the best P1\,dB of 20 dBm and PAE of 30% are demonstrated to verify the design concepts. This PA also shows the widest fractional bandwidth performance among CMOS PAs below 10 GHz. [ABSTRACT FROM AUTHOR]

This letter demonstrates a 22–31 GHz CMOS distributed amplifier (DA) based on high-pass transmission lines. Unlike the low-pass DA, the circuit can be smaller since it does not need extra drain bias circuits. This DA has a maximum output power of 12 dBm, a maximum OP1dB of 6.5 dBm, and a small signal gain of 6.4 dB. The chip occupies a miniature area of 0.28 mm^2 including the pads and the core area is only 0.17 mm^2. [ABSTRACT FROM PUBLISHER]

There is an error in the order of the references [18] and [19] in the above-named article [ibid., vol. 61, no. 4, pp. 1533?1542, Apr. 2013]. The order of these references should be exchanged. The corrected order (and numbering) of these two references are shown as follows: [18] J. Kim and J. F. Buckwalter, "A 92 GHz bandwidth distributed amplifier in a 45 nm SOI CMOS technology," IEEE Microw. Wireless Compon. Lett., vol. 21, no. 6, pp. 329?331, Jun. 2011. [19] A. Jahanian and P. Heydari, "A CMOS distributed amplifier with distributed active input balun using GBW and linearity enhancing techniques," IEEE Trans. Microw. Theory Techn., vol. 60, no. 5, pp. 1331?1341, May 2012. [ABSTRACT FROM PUBLISHER]