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As deep neural networks (DNNs) continue to find applications in ever more domains, the exact nature of the neural network architecture becomes an increasingly sensitive subject, due to either intellectual property protection or risks of adversarial attacks. While prior work has explored aspects of the risk associated with model leakage, exactly which parts of the model are most sensitive and how one infers the full architecture of the DNN when nothing is known about the structure a priori are problems that have been left unexplored. In this paper we address this gap, first by presenting a schema for reasoning about model leakage holistically, and then by proposing and quantitatively evaluating DeepSniffer, a novel learning-based model extraction framework that uses no prior knowledge of the victim model. DeepSniffer is robust to architectural and system noises introduced by the complex memory hierarchy and diverse run-time system optimizations. Taking GPU platforms as a showcase, DeepSniffer performs model extraction by learning both the architecture-level execution features of kernels and the inter-layer temporal association information introduced by the common practice of DNN design. We demonstrate that DeepSniffer works experimentally in the context of an off-the-shelf Nvidia GPU platform running a variety of DNN models and that the extracted models significantly improve attempts at crafting adversarial inputs. The DeepSniffer project has been released in https://github.com/xinghu7788/DeepSniffer. [ABSTRACT FROM AUTHOR]

Machine Learning Computers (MLCs) with tensor functional units (e.g., NVIDIA’s Tensor Core, Google’s TPU and Habana’s Tensor Processor Core) have emerged significantly over recent years. The broad diversity of MLCs makes it hard to deploy machine learning workloads with optimized performance. Though deep learning compilers (e.g., TVM) are effective to produce optimized code for different hardware back-ends, when deploying to a new MLC, it is tedious to implement platform-specific compilation optimizations by thoroughly understanding system/architectural details. To address this problem, we propose a holistic approach to achieve one-size-fits-all compilation optimization for inference across different MLCs. The key observation is that diverse MLCs share multiple key architectural characteristics (e.g., tensor primitives and on-chip scratchpad memory) for tensor processing, which can be generalized for conducting cross-platform compilation optimizations. Concretely, we propose the Tensor Abstract Machine (TAM), which features such common architectural characteristics, as the abstraction of a broad range of MLCs. To leverage architectural characteristics of the TAM, we propose the Tensor Scheduling Language (TSL) consisting of tensor computation description and tensor scheduling primitives for implementing operations with portable optimization. By implementing tensor operations with TSL, the related optimized code for different MLCs can be automatically generated. To validate our proposal, we conduct experiments on 3 commodity MLCs including GPU with Tensor Cores, VTA (on FPGA), and Cloud TPU. Experimental results demonstrate that the code generated from the same optimization schedule achieves 1.05x to 2.05x better performance than hand-tuned libraries and deep learning compilers across different platforms. [ABSTRACT FROM AUTHOR]

Graph neural networks (GNNs), which extend traditional neural networks for processing graph-structured data, have been widely used in many fields. The GNN computation mainly consists of the edge processing to generate messages by combining the edge/vertex features and the vertex processing to update the vertex features with aggregated messages. In addition to nontrivial vector operations in the edge processing, huge random accesses and neural network operations in the vertex processing, the graph topology of GNNs may also vary during the computation (i.e., dynamic GNNs). The above characteristics pose significant challenges on existing architectures. In this article, we propose a novel accelerator named CAMBRICON-G for efficient processing of both dynamic and static GNNs. The key of CAMBRICON-G is to abstract the irregular computation of a broad range of GNN variants to the process of regularly tiled adjacent cuboid (which extends the traditional adjacent matrix of graph by adding the dimension of vertex features). The intuition is that the adjacent cuboid facilitates exploitation of both data locality and parallelism by offering multidimensional multilevel tiling (including spatial and temporal tiling) opportunities. To perform the multidimensional spatial tiling, the CAMBRICON-G architecture mainly consists of the cuboid engine (CE) and hybrid on-chip memory. The CE has multiple vertex processing units (VPUs) working in a coordinated manner to efficiently process the sparse data and dynamically update the graph topology with dedicated instructions. The hybrid on-chip memory contains the topology-aware cache and multiple scratchpad memory to reduce off-chip memory access. To perform the multidimensional temporal tiling, an easy-to-use programming model is provided to flexibly explore different tiling options for large graphs. Experimental results show that compared against Nvidia P100 GPU, the performance and energy efficiency can be improved by $7.14\times $ and $20.18\times $ , respectively, on various GNNs, which validates both the versatility and energy efficiency of CAMBRICON-G. [ABSTRACT FROM AUTHOR]

Emerging resistive random access memory (RRAM) has shown the great potential of in-memory processing capability, and thus attracts considerable research interests in accelerating memory-intensive applications, such as neural networks (NNs). However, the accuracy of RRAM-based NN computing can degrade significantly, due to the intrinsic statistical variations of the resistance of RRAM cells. In this article, we propose SIGHT, a synergistic algorithm-architecture fault-tolerant framework, to holistically address this issue. Specifically, we consider three major types of faults for RRAM computing: 1) nonlinear resistance distribution; 2) static variation; and 3) dynamic variation. From the algorithm level, we propose a resistance-aware quantization to compel the NN parameters to follow the exact nonlinear resistance distribution as RRAM, and introduce an input regulation technique to compensate for RRAM variations. We also propose a selective weight refreshing scheme to address the dynamic variation issue that occurs at runtime. From the architecture level, we propose a general and low-cost architecture accordingly for supporting our fault-tolerant scheme. Our evaluation demonstrates almost no accuracy loss for our three fault-tolerant algorithms, and the proposed SIGHT architecture incurs performance overhead as little as 7.14%. [ABSTRACT FROM AUTHOR]

Deep neural network (DNN) accelerators are widely deployed in computer vision, speech recognition, and machine translation applications, in which attacks on DNNs have become a growing concern. This article focuses on exploring the implications of hardware Trojan attacks on DNNs. Trojans are one of the most challenging threat models in hardware security where adversaries insert malicious modifications to the original integrated circuits (ICs), leading to malfunction once being triggered. Such attacks can be conducted by adversaries because modern ICs commonly include third-party intellectual property (IP) blocks. Previous studies design hardware Trojans to attack DNNs with the assumption that adversaries have full knowledge or manipulation of the DNN systems’ victim model and toolchain in addition to the hardware platforms, yet such a threat model is strict, limiting their practical adoption. In this article, we propose a memory Trojan methodology that implants the malicious logics merely into the memory controllers of DNN systems without the necessity of toolchain manipulation or accessing to the victim model and thus is feasible for practical uses. Specifically, we locate the input image data among the massive volume of memory traffics based on memory access patterns and propose a Trojan trigger mechanism based on detecting the geometric feature in input images. Extensive experiments show that the proposed trigger mechanism is effective even in the presence of environmental noises and preprocessing operations. Furthermore, we design and implement the payload and verify that the proposed Trojan technique can effectively conduct both untargeted and targeted attacks on DNNs. [ABSTRACT FROM AUTHOR]

In order to reduce the computational complexity of convolutional neural networks (CNNs), the local binary convolutional neural network (LBCNN) has been proposed. In the LBCNN, a convolutional layer is divided into two sublayers. Sublayer 1 is a sparse ternary-weighted convolutional layer, and Sublayer 2 is a 1 × 1 convolutional layer. With the use of two sublayers, the LBCNN has lower computational complexity and uses less memory than the CNN. In this brief, we propose a platform that includes a weight preprocessor and layer accelerator for the LBCNN. The proposed weight preprocessor takes advantage of the sparsity in the LBCNN and encodes the weight offline. The layer accelerator effectively uses the encoded data to reduce computational complexity and memory accesses for an inference. When compared to the state-of-the-art design, the experimental results show that the number of clock cycles are reduced by 76.32%, and memory usage is reduced by 39.41%. The synthesized results show that the clock period is reduced by 4.76%; the cell area is reduced by 46.48%, and the power consumption is reduced by 40.87%. The inference accuracy is the same as that of the state-of-the-art design. [ABSTRACT FROM AUTHOR]

Tensor network and tensor computation are widely applied in scientific and engineering domains like quantum physics, electronic design automation, and machine learning. As one of the most fundamental operations for tensor networks, a tensor contraction eliminates the sharing orders among tensors and produces a compact sub-network. Different contraction sequence usually yields distinct storage and compute costs, and searching the optimal sequence is known as a hard problem. Prior work have designed heuristic and fast algorithms to solve this problem, however, several issues still remain unsolved. For example, the data format and data structure are not efficient, the constraints during modeling are impractical, the search of the optimal solution might fail, and the search cost is very high. In this paper, we first introduce a logk order representation and design an adjacency matrix-based data structure to efficiently accelerate the search of the optimal contraction sequence. Then, we propose an outer product pruning method with acceptable overhead to reduce the search space. Finally, we use a multithread optimization in our implementation to further improve the execution performance. We also present in-depth analysis of factors that influence the search time. This work provides a full-stack solution for optimal contraction sequence search from both high-level data structure and search algorithm to low-level execution parallelism, and it will benefit a broad range of tensor-related applications. [ABSTRACT FROM AUTHOR]

Time series is very ubiquitous in both the industrial environment and real-life. Capturing the time dependency is very useful for time series analysis. Although the one-dimensional local binary pattern (1D-LBP) can analyze the Univariate time series, it cannot effectively handle the multivariate time series (MTS). The UTS can be considered as zero-order tensor time series (TTS), while the MTS can be considered as one- or higher order TTS. Each variable in MTS depends not only on its past values, but also on the other variables. In this article, we propose a temporal tensor LBP (TTLBP) operator to extract the discriminative temporal features from TTS by extending 1D-LBP operation from the scalar-wise to the tensor-wise. The TTLBP is discriminative and can handle the TTS effectively and straightforwardly. To the best of our knowledge, TTLBP is the first LBP variant for TTS analysis. Furthermore, we also propose a stricter uniform TTLBP to improve robustness and to reduce the high dimensionality. We apply the proposed TTLBP in the edge intelligence-assisted video anomaly detection system. Qualitative and quantitative comparisons demonstrate the effectiveness of the proposed TTLBP. [ABSTRACT FROM AUTHOR]

Toward the long-standing dream of artificial intelligence, two successful solution paths have been paved: 1) neuromorphic computing and 2) deep learning. Recently, they tend to interact for simultaneously achieving biological plausibility and powerful accuracy. However, models from these two domains have to run on distinct substrates, i.e., neuromorphic platforms and deep learning accelerators, respectively. This architectural incompatibility greatly compromises the modeling flexibility and hinders promising interdisciplinary research. To address this issue, we build a unified model description framework and a unified processing architecture (Tianjic), which covers the full stack from software to hardware. By implementing a set of integration and transformation operations, Tianjic is able to support spiking neural networks, biological dynamic neural networks, multilayered perceptron, convolutional neural networks, recurrent neural networks, and so on. A compatible routing infrastructure enables homogeneous and heterogeneous scalability on a decentralized many-core network. Several optimization methods are incorporated, such as resource and data sharing, near-memory processing, compute/access skipping, and intra-/inter-core pipeline, to improve performance and efficiency. We further design streaming mapping schemes for efficient network deployment with a flexible tradeoff between execution throughput and resource overhead. A 28-nm prototype chip is fabricated with >610-GB/s internal memory bandwidth. A variety of benchmarks are evaluated and compared with GPUs and several existing specialized platforms. In summary, the fully unfolded mapping can achieve significantly higher throughput and power efficiency; the semi-folded mapping can save 30x resources while still presenting comparable performance on average. Finally, two hybrid-paradigm examples, a multimodal unmanned bicycle and a hybrid neural network, are demonstrated to show the potential of our unified architecture. This article paves a new way to explore neural computing. [ABSTRACT FROM AUTHOR]

A vaccine is a biological product which is an important means for human beings to protect themselves. Most of its users are young children with weak immunity. Once a vaccine has a problem, it will pose a serious threat to the lives of many people. At present, the supervision of vaccine production is very simple. The vaccine production record is completely controlled by the enterprises. Enterprises only submit production records to the supervisory agency for review when the vaccine needs to be sold. Production records are easily forged and modified. In order to solve the shortcomings of traditional centralized management. We propose a supervision method for vaccine production based on double-level blockchain. At first, we have designed a double-level blockchain structure. The first level is private data of vaccine prduction enterprise, including production records and corresponding hash. The next level is public data, including production records hash and vaccine information. In this way, we make vaccine enterprise to submit production records in a timely manner without fear of privacy leaks. We avoid enterprise tampering or falsification of production records through the non-tampering features and time stamps of the blockchain. To improve the time efficiency, we propose a consensus mechanism for multi-node cooperate. The primary supervisory node provides sorting services and verifies the correctness of the blockchain replica. The ordinary supervisory node can replace the primary supervisory node when necessary, and help the primary supervisory node recovers data in case of information loss. The review node is responsible for providing complete and correct blockchain copies for other nodes. So we can avoids the problem of waste of time resources in the traditional blockchain system. In addition, in order to avoid the waste of space caused by the redundancy of the blockchain, we propose a vaccine data cutting mechanism. We use the timestamp of the blockchain and the vaccine validity period to determine if the block can be cutted. At the same time, it is also possible to judge whether the block can be cutted based on the information exchange with the vaccination institution. Through these methods, we have realized spatiotemporal efficiency supervision of vaccine production. And for the time being, research work in the field of vaccine production supervision is still very rare. So Our work is ground-breaking. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC) has been one of the most popular candidates in high-voltage applications. However, reliability is a critical issue due to a large number of power switching devices and capacitors applied in the MMC. To improve the reliability of the MMC, a fast and reliable diagnosis strategy for the open-circuit fault is proposed in this paper, where submodule voltage sensors are relocated to the upper switching device. Furthermore, a voltage observer based on the submodule voltage sensor is established to monitor the capacitor and realize the power control of the MMC under normal operation. A Boolean logic operation based fault indicator is put forward based on the relationship of the operation state and binaried output of voltage sensors, which could detect and locate the open-circuit faults of the MMC very fast. The ratio of the increment of the observed and measured capacitor voltage during the period of positive arm current is applied to monitor the capacitor. The effectiveness of the proposed fault diagnosis strategy and the capacitor monitoring strategy is verified by the experiment results. [ABSTRACT FROM AUTHOR]

A brushless doubly fed generator (BDFG) for wind power applications with a double-rotor structure is presented in this paper. First, field modulation ring and its application in the proposed BDFG are introduced. The geometric constraints of the field modulation ring are analyzed. Then, the operation principle of a variable-speed constant-frequency BDFG system is presented. The design of the BDFG is discussed, and finite-element analysis for the BDFG is carried out to obtain the performance of the machine. Finally, a small-size prototype machine is designed and manufactured to verify the theoretical analysis. The proposed BDFG has some advantages, such as high efficiency and high reliability. It has good potential on the applications of future large-scale wind power generation systems. [ABSTRACT FROM AUTHOR]