11 results on '"Holsteyns F"'
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2. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
3. A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation
4. First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs
5. Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition
6. Development of an all-in one wet single wafer process for 3D-SIC bump integration and its monitoring
7. Integrated clean for TSV: Comparison between dry process and wet processes and their electrical qualification
8. First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs.
9. Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal
10. Roadblocks and Critical Aspects of Cleaning for Sub-65nm Technologies
11. Monitoring and qualification using comprehensive surface haze information.
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