174 results on '"Hoffmann, T"'
Search Results
2. Broadband Driver Amplifier with Voltage Offset for GaN-based Switching PAs
3. Impact of Drain-Lag Induced Current Degradation for a Dynamically Operated GaN-HEMT Power Amplifier
4. Wideband Dynamic Drain Current Measurements with a Galvanically Isolated Probe Targeting Supply-Modulated RF Power Amplifiers for 5G Infrastructure
5. A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits
6. Analysis of dopant diffusion and defects in SiGe channel Quantum Well for Laser annealed device using an atomistic kinetic Monte Carlo approach
7. 3D-carrier profiling in FinFETs using scanning spreading resistance microscopy
8. Dopant and carrier profiling for 3D-device architectures
9. Picosecond pulses with more than 60 W peak power generated by a singlestage all-semiconductor master-oscillator power-amplifier system
10. Simple current and capacitance methods for bulk finFET height extraction and correlation to device variability
11. On the recoverable and permanent components of Hot Carrier and NBTI in Si pMOSFETs and their implications in Si0.45Ge0.55 pMOSFETs
12. On the origin of the mobility reduction in bulk-Si, UTBOX-FDSOI and SiGe devices with ultrathin-EOT dielectrics
13. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
14. An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations
15. High-mobility 0.85nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD
16. Analysis of pocket profile deactivation and its impact on Vth variation for Laser annealed device using an atomistic kinetic Monte Carlo approach
17. Low-frequency noise in strained and relaxed Ge pMOSFETs
18. Dopant and carrier profiling in FinFET-based devices with sub-nanometer resolution
19. High-mobility Si1−xGex-channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths
20. Ion-implantation-based low-cost Hk/MG process for CMOS low-power application
21. Laser annealed junctions: Pocket profile analysis using an atomistic kinetic Monte Carlo approach
22. 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS
23. Laser driver switching 20 A with 2 ns pulse width using GaN
24. Key sub 1nm EOT CMOS enabler by comprehensive PMOS design
25. Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization
26. Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution
27. Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology
28. Review of FINFET technology
29. Comprehensive characterization of BEOL-TDDB performance using very fast Voltage ramp Dielectric Breakdown tests
30. Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?
31. Impact of Epi-Si growth temperature on Ge-pFET performance
32. Junction anneal sequence optimization for advanced high-k / metal gate CMOS technology
33. Fundamental study on the impact of C co-implantation on ultra shallow B juntions
34. Single-Metal Dual-Dielectric (SMDD) gate-first CMOS integration towards low VT and high performance
35. High-k/ metal-gate stack work-function tuning by rare-earth capping layers: Interface dipole or bulk charge?
36. Carbon-based thermal stabilization techniques for junction and silicide engineering for high performance CMOS periphery in memory applications
37. Processing impact on the reliability of single metal dual dielectric (SMDD) gate stacks
38. Positive and negative bias temperature instability in La2O3 and Al2O3 capped high-k MOSFETs
39. Advanced 2D/3D simulations for laser annealed device using an atomistic kinetic Monte Carlo approach and Scanning Spreading Resistance Microscopy (SSRM)
40. Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell
41. Control of laser induced interface traps with in-line corona charge metrology
42. Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability
43. Fundamentals and extraction of velocity saturation in sub-100nm (110)-Si and (100)-Ge
44. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
45. Low VT metal-gate/high-k nMOSFETs — PBTI dependence and VT Tune-ability on La/Dy-capping layer locations and Laser annealing conditions
46. Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal
47. Impact of sub-melt laser annealing on Si1-xGex source /drain defectivity
48. Widening of FUSI RTP Process Window by Spike Anneal
49. Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT
50. Laser Annealed Junctions: Process Integration Sequence Optimization for Advanced CMOS Technologies
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.