Search

This paper presents a power-efficient Ultra Low Voltage (ULV) Fully-Differential (FD) Digital-Based Operational Transconductance Amplifier for Biomedical signal processing (BioDIGOTA), which digitally processes biological analog signals using CMOS standard-cells. Post-layout simulations, including parasitic effects in 180nm CMOS technology, show that BioDIG- OTA consumes only 144 nW at 300 mV of supply voltage while driving a 20 pF capacitive load, with a power efficiency factor (PEF) lower than 1. The layout occupies 0.03 mm2 total silicon area, excluding I/0 pads. The proposed BioDIGOTA proves that digital-based analog design can be adopted in biomedical signal amplifiers, lowering the total silicon area by 2.3X times compared to the current state of the art landscape while keeping reasonable power and system performance.

An ultra-low voltage and ultra-low power Digital-Based Operational Transconductance Amplifier (DB-OTA) is presented and demonstrated on silicon in 180 nm CMOS. The DB-OTA is designed using digital standard cells, hence benefitting from technology scaling as much as digital circuits, while also being technology- and design-portable, and requiring minimal design and integration effort compared to conventional analog-intensive OTAs. The fabricated DB-OTA testchip occupies a compact area of 1,426 $\mu \text{m}^{2}$ , operates at supply voltages down to 300 mV, and consumes only 590 pW while driving a capacitive load of 80pF. Its measured Total Harmonic Distortion (THD) is lower than 5% at a 100-mV input signal swing. Based on these results, the proposed DB-OTA achieves 2,101 V−1 small-signal figure of merit (FOMS) and 1,070 large-signal figure of merit (FOML). To the best of the authors’ knowledge, the power is the lowest reported to date in an OTA, and the achieved figures of merit are the best in sub-500 mV OTAs reported to date. The low cost, the low design effort and the high power efficiency of DB-OTA make it well suited for purely harvested low-frequency analog interfaces in sensor nodes.

This paper presents a non-linear shunt regulator based on a PWM RF power detector for RFID applications. The shunt regulator is composed of two feedback loops. The first is a fast loop based on a simple RF voltage clamp that guarantees overvoltage protection for the internal circuits. The second is an accurate loop based on a power detector circuit that slowly corrects the first loop errors according to the input RF power. The theoretical formulation of the RF-to-DC conversion in the power detector is presented and compared to a high-level implementation. A small-signal model of the complete shunt regulator was developed to assist in the CMOS circuit design. The regulator is part of a commercial low-frequency RFID transponder. It shows an improvement of 16.7 % in the maximum communication distance of the transponder with the shunt regulator enabled when compared to the previous power limiting approach using only clamping diodes.

This work presents the analysis, design, and performance evaluation of three usual CMOS proportional to absolute temperature (PTAT) voltage generators, with emphasis on variability effects. Minimization or compensation of the main error sources, such as fabrication variability and intrinsic non-linearities, is an important design challenge required to increase the precision and robustness of a voltage reference. The CMOS PTAT topologies are analytically described and design methodologies for PTAT circuits in subthreshold are presented. The compromises between design conditions and resulting performance are evaluated through simulation for these three PTAT generators, including linearity with temperature, temperature coefficient (TC), and variability impact. Monte-Carlo simulations demonstrated the sensitivity of each topology to fabrication variability, showing that the self-cascode MOSFET structure presents the best accuracy of TC, nominal PTAT voltage, and linearity with temperature.

This work presents the design of a MOS-only voltage reference with nano-watt power consumption. The proposed circuit consists of a threshold voltage monitor circuit cascaded with a high-slope proportional to absolute temperature (PTAT) voltage generator. The operation of the circuit is analytically described and a design methodology is presented. The proposed circuit was designed and simulated in a standard 130 nm CMOS process while consuming just 37 nW under 1.2 V of power supply at room temperature. Simulation results present a 585 mV reference voltage with a typical temperature coefficient (TC) of 10.13 ppm/°C, for a temperature range from −40 to 125 °C, a power supply rejection ratio (PSRR) of −54.41 dB at 100 Hz, and a line sensitivity of 0.071 %/V was found for a supply range from 1 V to 1.8 V. Monte-Carlo simulations are presented to evaluate the sensitivity to fabrication variability. The estimated silicon area is 0.0078 mm2.

This paper presents a fully-integrated 32.7 kHz relaxation oscillator designed in TSMC 40 nm CMOS for IoT applications. Simulation results show that the proposed relaxation oscillator consumes 40 nW at room temperature from 0.6 V power supply. The architecture achieves a temperature coefficient (TC) as low as 12.5 ppm/°C (μ = 35.5 ppm/°C for 400 samples) from −40°C to 125°C. Also, more than 50% of samples have a TC less than 30 ppm/°C. The oscillator also has a fast start-up time, achieving a steady-state of the operating frequency within 3 cycles. The energy efficiency is 1.22 nW/kHz, and the entire circuit occupies an active area of 0.127 mm2.

The Relaxation oscillators (ROSCs) offer a better trade-off between power consumption, physical area and accuracy. This paper presents a study of recently published ultra-low-power relaxation oscillators with low-temperature coefficient, identifying its characteristics, performance parameters, and main challenges. A brief review show as state-of-the-art circuits handle with PVT (Process, voltage, and temperature) variations. By the end of this analysis, some trends in relaxation oscillators design are discussed.

This work presents the design of a narrowband Low Noise Amplifier (LNA) that is a part of a transponder project of a UHF satellite for the Brazilian Environmental Data Collecting System (SBCDA). The proposed LNA operates at 401.635 MHz moreover, it provides 28dB of power gain, 3.6dB of noise figure (NF), IIP3 of -28 dBm and 6.53 mW of power consumption and it was designed in a standard 130 nm CMOS process.

This paper presents a power-efficient Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifier (DB-OTA), which uses static logic gates and processes digitally the analog input signal. Post-layout simulations in 180nm CMOS technology show that at 300mV supply voltage the circuit consumes just 2nW while driving a capacitive load of 80pF with Total Harmonic Distortion lower than 5% at 100mV input signal swing. The total silicon area is $1,426\ \mu \mathrm{m}^{2}$ . The maximum energy efficiency supply for the DB-OTA and its scalability to 40nm CMOS technology node are also demonstrated.

A voltage reference based on MOSFETs operated under Zero Temperature Coefficient (ZTC) bias is proposed. The circuit operates in a power supply voltage range from 0.3 V up to 1.2 V and outputs three different reference voltages using Standard- $V_{T}$ (SVT), Low- $V_{T}$ (LVT), and Zero- $V_{T}$ (ZVT) MOS transistors biased near their ZTC point by a single PTAT current reference. Measurements on 15 circuit samples fabricated in a standard 0.13- $\mu \text{m}$ CMOS process show a worst-case normalized standard deviation $(\sigma /\mu)$ of 3% (SVT), 5.1% (LVT) and 10.8% (ZVT) respectively with a 75% of confidence level. At the nominal supply voltage of 0.45 V, the measured effective temperature coefficients (TCeff) range from 140 to 200 ppm/°C over the full commercial temperature range. At room temperature (25 °C), line sensitivity in the ZVT VR is just 1.3%/100 mV, over the whole supply range. The proposed reference draws around 5 $\mu \text{W}$ and occupies 0.014 mm2 of silicon area.

This work presents an ultra-low power low-voltage high-order temperature-compensated voltage reference. The proposed circuit is based on the self-cascode MOSFET (SCM) and explores the dependence of the threshold voltage (V T ) with the transistor dimensions. The SCM is biased by the leakage current of a zero-V T transistor for PSRR improvement. The proposed circuit is composed only of 3 transistors. The high-order temperature compensation is achieved through a bulk-driven scheme. Additionally, the proposed high-order compensation also attenuates the mismatch variability of the voltage reference. Post-layout simulation results for a standard 130 nm CMOS process are presented. A voltage reference of 90.5 mV with a 1 ppm/°C temperature coefficient (TC) is achieved at typical corner. The circuit can operate at a minimum supply voltage as low as 0.3 V while consuming 43.7 pW at room temperature.

This work presents a fully integrated single-stage 2.4 GHz power amplifier (PA) that was designed in a 180nm CMOS process using a power combining technique to achieve higher output power. A series combining transformer (SCT) combines two cascode differential amplifiers and makes extensive use of virtual AC ground nodes to reduce the impact of bond-wire parasitics. The center-taps of the output transformers are used for 2nd harmonic impedance tuning inside the chip. In post-layout simulation the PA uses a 3.3 V power supply and achieves 24dBm maximum output power at a peak drain efficiency of 23.4%. The test chip returned recently from fabrication and it will undergo electrical tests soon.

A nano-ampere current reference with temperature compensation operating is presented. The reference current is generated biasing a zero-VT transistor near its Zero-temperature coefficient (ZTC) point. Two versions were implemented in a 180 nm CMOS process. Both are designed using the same thermal compensation principle, but the second version uses an auxiliary circuit to compensate process variation. The circuits occupy 0.01 and 0.018 mm2 of silicon area while consuming around 30.5 and 122 nW at 27° C, respectively. Post-layout simulations present a reference current of 10.86 and 10.95 nA with a average temperature coefficient of 108 and 127 ppm/°C (100 Samples), under a temperature range from −20 to 120 °C, and a line sensitivity of 0.54 and 0.86 %/V at 0.9 V to 1.8 V of supply voltage, respectively.

This work presents a six phase Switched Capacitor (SC) DC — DC converter for photovoltaic Energy Harvesting designed in a 130 nm CMOS process for commercial motes application and Internet of Things (IoT). It tracks the Maximum Power Point (MPP) of a commercial 3 cm × 3 cm 60 mW poly-crystalline photoelectric panel through switching frequency modulation aiming battery recharge. Open-circuit voltage ratio was the chosen Maximum Power Point Tracking (MPPT) strategy. The converter achieves a maximum power conversion efficiency of 90 % for input power higher than 30 mW and is designed to operate with input voltages from 1.25 V to 1.8 V, resulting output voltages from 2.5 V to 3.6 V, respectively. Peripheral circuitry also includes an output over-voltage protection of 3.6 V and the control circuits, that consumes a total of 850 μA at 3.3 V. Complete layout consumes 300 × 700 μm2 of silicon area. The only external components are 6×100 nF capacitors.

This paper presents a 300 MHz to 3 GHz Low-Noise Amplifier (LNA) with high HP3 and one of the smallest silicon area we could find. It is based on a single amplifier, where it is systematically optimized to achieve better results than more complex noise canceling topologies, thus, saving area and power consumption. A CMOS inverter with resistive feedback where transistors are self-biased in strong inversion is designed and optimized for low NF and high IIP3 and then the feedback resistor is calculated for input impedance matching. The post-layout simulation results in a 130 nm process show for the entire bandwidth a voltage gain around 12 to 15 dB, a NF < 3.6 dB, a Sii of −15.2 to −10.5 dB, HP3 of 4.7 to 5.3 dBm, total area of 40 um × 30 um and power consumption of 6.5 mW under 1.2 V supply. Monte Carlo simulations for 1000 samples show IIP3 of 3.3 to 6 dBm with σ of 0.48 dBm.

This paper presents a self-biased self-cascode MOSFET (SBSCM) voltage reference that can operate with supply voltages as low as 0.45 V while consuming tens of pW. The voltage reference is generated through the self-cascode MOSFET (SCM) using transistors with different threshold voltages and is implemented in a way that the SCM itself composes the bias circuitry. The proposed topology was implemented in a standard 0.18 μm CMOS process and post-layout simulation results in a reference voltage of 248 mV with temperature coefficient around 7 ppm/oC for the 0 oC to 125 oC range, while consuming 93 pW at room temperature with 0.45 V of supply voltage. The occupied silicon area is 0.002 mm2.

The design of an ultra-low voltage CMOS wideband LNA topology operating under a 0.6 V power supply with high gain and high IP2 is presented in this paper. The circuit performance is targeted towards use in direct conversion receivers, where a high IP2 is required. The LNA operates in sub-1 GHz applications reaching frequencies as low as 50 MHz, as it is required by IEEE 802.22 standard. The topology proposed here is based on the resistive-feedback inverter with a cascaded auxiliary amplifier to implement noise canceling. This cascaded amplifier is composed by a common-source (CS) amplifier and a very linear buffer at the output of the cascade. The high IP2 is obtained by a proper transistor biasing and by combining diodes with the load of the amplifiers with the highest non-linearity. This topology also works as a balun to comply with single-ended input from antennas and differential mixers as output loads. The post-layout simulations included bondwire inductances and pad capacitances parasitics. The results show a bandwidth of 50 MHz–1 GHz, voltage gain > 18 dB, NF < 3.8 dB, Sn < −13 dB and maximum IP2 of 38 dBm. The LNA power consumption is just 6.7 mW, excluding pad buffers.

In this paper, we present a VCO designed for operation at 250 mV dissipating 590 nW, free running frequency of 462 kHz with voltage-to-frequency maximum non-linearity of 0.33%. The VCO design aim to a time based ADC, whose resolution is highly limited by the non-linearity of the VCO itself, which may be corrected by further digital calibration. The proposed VCO uses a ring oscillator topology and employs forward body biasing to achieve high linearity in the analog domain.

This paper presents a MOS-only high power supply rejection (PSRR) voltage reference with a very low temperature coefficient (TC) that consumes only tens of nano-Watt. It is composed by a threshold voltage monitor circuit with no resistors, cascaded with a thermal voltage generator, adequate for fabrication in standard processes. Since the MOS transistors operate in subthreshold and near-threshold regimes the current consumption is very low. The operation of the circuit is analytically described and a design methodology is proposed. Post-layout simulations for a design in a 130 nm CMOS process are presented, resulting a reference voltage around 670 mV with a best case TC of 1.5 ppm/°C for the −40 to +125 °C range and an average TC of 20 ppm/°C over process variations, untrimmed. A very low sensitivity to VDD is achieved, resulting a PSRR lower than −71 dB at 100 Hz and a line sensitivity (LS) lower than 576 ppm/V for a supply range from 1 to 3 V. The area is very small, 0.0084 mm2 including the start-up stage.

In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the picowatt range and occupies very small area is proposed. The circuit is based on a self-cascode structure that is biased in subthreshold condition using the leakage current provided by a reverse biased MOSFET diode. Its electrical behavior is analytically described and a design methodology is presented to allow the transistors sizing for optimal temperature compensation. Simulation results for a standard 130 nm CMOS process are presented to validated the proposed circuit topology. A reference voltage of 85 mV is obtained with a temperature coefficient (TC) of 17.4 ppm/°C and consuming only 7 pW under 0.3 V of power supply at room temperature. Monte Carlo analysis shows that the reference voltage σ/μ< 3.3% and that 90% of the samples present TC

The analysis and design of a resistorless sub-bandgap voltage reference using Schottky diode and Low-VTo transistors is presented herein. The circuit is self-biased and works in the nano-ampere consumption range, achieving full operation at 0.3 V of supply voltage. The design is validated through post-layout simulations including process variability analysis, for a commercial 130 nm CMOS process. A voltage reference of 102.8 mV is reached under Vdd = 1.2V and 92.5 mV for VDD = 0.3V, with a temperature coefficient (TC) of 215.7 ppm/°C and 216 ppm/°C, respectively using curvature correction to improve the TC in the range from −40° C to 120° C. The current consumption is 212 nA with VDD = 1.2V at 27°C, and the chip area is 0.0068 mm2.

This paper proposes a 2.2 GHz CMOS Power Amplifier (PA) useful to S-Band applications with an effective 3-bit output power control for efficiency improvement. It uses an input transformer to reduce ground bounce effects and operates around 1 W of output power. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) of 3 branches is separately activated by a 3-bit input. The classE power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF process and post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 47% under 3.3 V of supply voltage. The 3-bit control allows a total output power dynamic range adjustment of 12.4 dB, divided in 8 steps, with the PAE changing from 13.4% to 47.3%.

This paper presents an alternative to crystal based oscillators for reference frequencies in highly integrated SoCs. The frequency reference through the usage of an active bias controlled ring oscillator operating with a supply voltage from 300 to 500 mV for an temperature from −40 to 125 ° C. The oscillator shows a very good temperature and supply voltage frequency stability coming from the active biasing using a stable current reference.

This work presents the design of a 6 bits M-2M ladder Digital-to-Analog Converter (DAC) proper for operation under supply voltages of 200 mV or lower. Since the MOS transistors are operating in the subthreshold region under such low supply, the mismatch analysis was done using an all-region continuous MOSFET model. The performance of the circuit is evaluated through simulations and the trade-offs between linearity, supply voltage and sampling rate are investigated in the paper. It is proposed that a 6 bits M-2M DAC operating under 200 mV and with sampling rate of 5.1MS/s is feasible using a commercial 130 nm process and standard transistors.

This paper proposes a 2.2 GHz CMOS Power Amplifier (PA) useful to S-Band applications with an effective 3-bit output power control for efficiency improvement. It is composed by a cascode amplifier topology to minimize the voltage stress across the power transistors, being the cascode amplifier composed by four parallel branches, where the state (on or off) of 3 branches is separately activated by a 3-bit input, for efficiency control. It was designed for the 1 W output power range in 130 nm CMOS process. Post-layout simulations resulted a peak output power of 28.1 dBm (near 650 mW) with a maximum output power efficiency around 43% under 3.3 V of supply voltage. The 3-bit control allows a total output power dynamic range adjustment of 5.7 dBm, divided in 7 steps, with the efficiency changing from 25.4% to 43.7%.

This work presents a self-biased MOSFET threshold voltage V T0 monitor. The threshold condition is defined based on a current-voltage relationship derived from a continuous physical model. The model is valid for any operating condition, from weak to strong inversion, and under triode or saturation regimes. The circuit consists in balancing two self-cascode cells operating at different inversion levels, where one of the transistors that compose these cells is biased at the threshold condition. The circuit is MOSFET-only (can be implemented in any standard digital process), and it operates with a power supply of less than 1 V, consuming tenths of nW. We propose a process independent design methodology, evaluating different trade-offs of accuracy, area and power consumption. Schematic simulation results, including Monte Carlo variability analysis, support the V T0 monitoring behavior of the circuit with good accuracy on a 180 nm process.

This work presents a study of the CMOS based R-2R ladder network (also called M-2M) Digital-to-Analog Converter (DAC) as a potential candidate for ultra-low voltage (ULV) applications, i.e. supply voltages VDD lower than 200mV. MOS transistors operate in subthreshold under such very low VDD, and the circuit analysis must be done using an all-region continuous MOSFET model. Simulation results in a commercial 130 nm process corroborate the presented analysis, showing that it is possible to implement this DAC topology for 6 to 8 bits operating under supply voltages from 70 mV to 140 mV.

This paper describes the design and implementation of a low-pass third-order single-loop single-bit continuous-time sigma-delta modulator (CT-SDM) in a 130 nm CMOS process. To reduce clock jitter effects and operational amplifiers requirements a non-return-to-zero (NRZ) digital-to-analog converter (DAC) pulse shape was employed. Post-layout simulation results indicate that the modulator achieves 56 dB of dynamic range, 57.31 dB of peak SNDR or 9.23 bits of effective resolution over a 1 MHz signal bandwidth with an oversampling ratio (OSR) of 64. The CT-SDM draws 5.91 mW from a 1.2 V power supply providing a figure-of-merit (FOM) of 4.93 pJ/conv. The CT-SDM core area is 0.31 mm2 and the chip was manufactured and will be soon characterized.

The MOSFET Zero Temperature Coefficient (ZTC) condition is a strategy that can be used to implement low temperature sensitivity circuits, such as current and voltage references. This condition is usually analyzed using the strong inversion quadratic MOSFET model. In this work we use a different approach, based on a continuous MOSFET model that can predict its behavior from weak to strong inversion. Based on this analysis, we verify that the ZTC point occurs from moderate to strong inversion for any CMOS process, since this point must occur for gate-source voltages larger than one threshold voltage. Also, a resistorless switched capacitor current reference based on the ZTC condition (ZSCCR), presenting low temperature coefficient (TC), is presented. The ZSCCR is designed in a 180 nm process, resulting a reference current of 5.88 µA under a supply voltage of 1.8 V, and occuping a silicon area around 0.010mm2. Results from circuit simulation show an effective temperature coefficient (TC eff ) of 60 ppm/°C from −45 to +85 °C and a power consumption of 63 µW.

In this work a novel resistorless sub-bandgap voltage reference (BGR) is introduced. It is a self-biased and small area topology that works in the nano-ampere current consumption range, and under 1 V of power supply. The analytical behavior of the circuit is described, and simulation results for a standard 0.18 μm CMOS process are analysed. A reference voltage of 479 mV is demonstrated, with a temperature coefficient of 8.79 ppm/oC for the 0 to 125 °C range, while the power consumption of the whole circuit is 4.86 nW under a 0.9 V power supply at 27 oC. The estimated silicon area is 0.0012 mm2.

This work presents a novel Switched-capacitor Bandgap Voltage Reference (SCBGR) circuit that dispenses entirely the use of resistors. The vEB negative drift and the thermal voltage (VT) positive drift voltages are both generated by the same PNP vertical bipolar transistor, avoiding diode mismatch problems. The current sources that are used to generate different junction current densities are averaged in the switching process, reducing their mismatch impact on the circuit performance. A switched-capacitor circuit stores and processes these voltages, generating the bandgap reference voltage after 5 clock cycles. Since capacitors are used instead of resistors, variability problems like average process spread and device mismatches are reduced. The proposed topology was designed and simulated in CMOS for 180 nm process. This paper presents a systematic comparison to the traditional dual-BJT BGR and demonstrates the better performance of this new topology with respect to the former. Monte Carlo simulation shows significantly lower spread resulting from variations in the output reference voltage and in its temperature coefficient (TC).

This paper presents a new approach for accurate M-2M MOSFET digital-to-analog converter (DAC) design. It describes a complete design methodology, where DAC inaccuracy is related to transistor geometry and bias through a powerful physics-based MOSFET mismatch model, very useful for hand design. Short-channel effects are also taken into account. Two versions of the converter were implemented in a 0.35 mum 3.3 V CMOS technology, and corroborate the theoretical development with statistical experimental results.

Component tolerances and mismatches due to process variations severely degrade the performance of bandgap reference (BGR) circuits. In this paper, the authors describe the design of a BGR considering the Pelgrom's mismatch model. The main purpose of our methodology is to convey the design to reach a good trade-off between area and mismatch. Implemented in standard 0.35mum CMOS technology, the circuit also includes a straightforward 4-bits trimming circuit to achieve more process variations independence. Its Monte Carlo temperature coefficient average is 40-ppm/degC and the reference output voltage average is 1.230V. The area of the BGR is 400x350mum2 due to our design matching requirements.

Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significantly impact manufacture costs by decreasing yield and so by including extra-circuits for adjustment. In this paper we propose a design methodology based on the Pelgrom's MOS transistor-mismatching model devices. Our main objective is to calculate the size of each component considering their relation between area and mismatching. Therefore, in order to validate our proposal methodology, we used as a design target a bandgap reference circuit fabricated in 0.35 mum CMOS technology. Its temperature coefficient attains an average value of 40ppm/degC and an average output voltage of 1,20714V. It also includes a straightforward 4-bits trim circuit to achieve more process independence variation. As a result of our methodology, the considerable area of 400 times 350 mum2 was occupied due to our matching design requirements

Most of the new generation compact models for the MOSFET have many commonalities since they are based on the same main approximations: gradual channel, charge-sheet, and depletion charge linearization. In this study we show that if we include some additional physics-consistent conditions for the MOSFET equations we obtain a very compact model that we call the advanced compact MOSFET (ACM) model. The core ACM model, design-oriented equations, parameter extraction, and a design example are presented.